layouts. Because the 1.8V domains are no longer within the pad
ring buses, they need to be connected together in the cell. These
internal lines were previously in the power routing cells.
verilog/rtl/, and creates all the layout files needed to represent
all unique combinations of defaults used in the file. Not done:
Modifying the top level layout to use the correct defaults (because
the top level layout does not yet exist).
three parameterized values used in the RTL verilog. Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
continuous ring of vccd and vssd. The clamp connections for the
vccd1/vssd1 and vccd2/vssd2 pads still need to be done, although
the pads themselves have been changed to the base cell, matching
the new verilog RTL.
an unconnected wishbone bus (unconnected inputs). Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
Tim Edwards
manarabdelaty