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caravel
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377 Commits

Author SHA1 Message Date
M0stafaRady c7df730c0a cocotb - ziping passed waves instead of removing them 2022-10-18 02:56:31 -07:00
M0stafaRady 55eaf936b0 Cocotb - add delay at the test mgmt_gpio_bidir test 2022-10-17 04:35:29 -07:00
M0stafaRady de11170ab2 fix syntax error at gl/gpio_signal_buffering.v 2022-10-17 00:55:12 -07:00
marwaneltoukhy 2d28c973ee added views for caravel with power routing 2022-10-16 19:08:56 -07:00
marwaneltoukhy 7ec1eeb010 Merge branch 'caravel_redesign' into caravel_redesign-top-level 2022-10-16 18:39:39 -07:00
Marwan Abbas 35ec52aa72
Merge pull request #260 from efabless/fix_top_buffers_again 
More changes to the GPIO buffer cell
 2022-10-17 03:35:25 +02:00
Tim Edwards 9f54b2ecec Added a gate-level version of gpio_signal_buffering derived from 
the RTL, but cleaned up for macro definitions;  this can be used
for LVS.  The decap cells were hand-edited in because there is
no way to devine them from the RTL source.
 2022-10-16 21:20:12 -04:00
Tim Edwards 69d353f65c Corrected the verilog and the layout for the caravan version of the 
signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
 2022-10-16 21:06:27 -04:00
Marwan Abbas 37d2a9d463 connected rest of buffers to power 2022-10-17 01:15:46 +02:00
kareem 2409207178 reharden: caravel 
~ add non functional blocks - like caravel_motto
 2022-10-16 15:44:27 -07:00
Marwan Abbas 04a55c695f
Merge pull request #252 from efabless/fix_top_buffers_again 
Adjustments to the top level buffering cells
 2022-10-16 23:38:13 +02:00
kareem 704f19b6c7 reharden: caravel 
~ correct placement for spare_logic_block
~ add changes from buffering macro
 2022-10-16 12:56:41 -07:00
Marwan Abbas 4a7031c479
Merge pull request #258 from efabless/cocotb 
Cocotb tests and script updates
 2022-10-16 19:10:49 +02:00
kareem 2a3493ed65 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 10:03:54 -07:00
M0stafaRady 0542485ae9 remove file buff_flash_clkrst.nl.v 2022-10-16 09:57:54 -07:00
M0stafaRady 8526aadd4a Revert "remove unpowered netlist" 
This reverts commit dd482cb099.
 2022-10-16 09:56:24 -07:00
Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals 
being buffered pass through the buffer macros.  Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
 2022-10-16 12:49:44 -04:00
kareem fc0701003c reharden: caravel 
- based on second iteration of the buffer macro
- change config with updated placement of spare logic macros
and power routing cell
 2022-10-16 06:58:46 -07:00
M0stafaRady 8aaeb5bad8 rearrange testlist to test most number of features as quickly as possible 2022-10-16 05:43:04 -07:00
mo-hosni 22dde425ac add mgmt_protect views and openlane files 2022-10-16 03:14:55 -07:00
M0stafaRady 55671cded1 fix bug at bit bang tests 2022-10-15 18:10:33 -07:00
Passant dd482cb099 remove unpowered netlist 2022-10-15 13:46:21 -07:00
M0stafaRady aac5408dfe initial version of debug test 2022-10-15 11:40:39 -07:00
M0stafaRady fb1259dd56 Fix gpio control block access in gatelevel 2022-10-15 09:30:11 -07:00
kareem 5d5d019ea1 Revert "add buff_flash_clkrst" 
This reverts commit 2675487322.
 2022-10-15 08:47:02 -07:00
mo-hosni 2675487322 add buff_flash_clkrst 2022-10-15 06:38:42 -07:00
M0stafaRady 2794932853 Merge branch 'caravel_redesign' into cocotb 2022-10-15 04:37:47 -07:00
M0stafaRady 4fe8416c85 Add time consumed to the txt file 2022-10-15 04:36:55 -07:00
Marwan Abbas 696eddcc7b
Merge branch 'caravel_redesign' into buff_power_connection 2022-10-15 13:34:21 +02:00
M0stafaRady 14ebfa5259 fix bug in bitbang_no_cpu_all_o testbench 2022-10-15 04:18:05 -07:00
Marwan Abbas 40c7776b57 added power connection to buffer rtl 2022-10-15 12:56:40 +02:00
Marwan Abbas 1559e7c41d
Merge pull request #240 from efabless/cocotb 
Cocotb script updates
 2022-10-15 11:55:41 +02:00
M0stafaRady 2d56c68ef2 fix script to not create directory annotation_logs 2022-10-15 02:54:35 -07:00
Marwan Abbas d025944505
Merge branch 'caravel_redesign' into buff_power_connection 2022-10-15 11:48:51 +02:00
M0stafaRady 9be1caa84d Merge branch 'caravel_redesign' into cocotb 2022-10-15 02:40:55 -07:00
M0stafaRady 83e692e176 Merge branch 'caravel_redesign' into cocotb 2022-10-15 02:28:00 -07:00
Marwan Abbas 316f2dbb58
Merge pull request #238 from mo-hosni/update_mgmt_protect 
Update mgmt protect
 2022-10-15 11:27:59 +02:00
Marwan Abbas 6c19140590 added power connection to buffer top level rtl 2022-10-15 11:27:30 +02:00
M0stafaRady 267dfd0965 Add new regression for gpios gpio_rtl and gpio_gl 2022-10-15 02:26:36 -07:00
M0stafaRady 16f55976a9 fix bug at generating new linker script for memory tests 2022-10-15 02:22:21 -07:00
mo-hosni 3361c8787d Add mgmt_protect views and openlane files 2022-10-15 01:46:22 -07:00
M0stafaRady 5d6af67724 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-14 17:13:23 -07:00
M0stafaRady 422bb26ca0 Optimize and update mem tests - script is generating new linker script for the test to be all to test the whole dff or dff2 memory 2022-10-14 17:12:45 -07:00
M0stafaRady 5e044fc505 Merge branch 'caravel_redesign' into cocotb 2022-10-14 16:18:53 -07:00
M0stafaRady 5f046793e4 update verify cocotb script to delete waves if test passed 2022-10-14 16:18:33 -07:00
passant5 8c0e4f7403
Merge branch 'caravel_redesign' into add_top_level_buffers 2022-10-15 00:28:14 +02:00
Passant 653e7fa561 update top-level rtl to resolve conflict with adding top level buffers between housekeeping and `gpio_control_block` https://github.com/efabless/caravel/pull/213 2022-10-14 15:02:16 -07:00
Passant f499b8b75f update top-level rtl with 7 pass through signals to be buffered inside the SoC 2022-10-14 13:11:42 -07:00
mo-hosni 0e01725608 add housekeeping views 2022-10-14 09:26:34 -07:00
Tim Edwards ac209d2397 Corrected a bunch of typos (different signal names used in the 
same file), errors (buffer output pin name, power supplies not
passed at the top level).  Corrected a major error that prevented
the use of the buffers in simulation, so this was not previously
verified by simulation.  The buffering has now been properly
verified.
 2022-10-14 10:51:29 -04:00