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caravel
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215 Commits

Author SHA1 Message Date
Mohamed Shalan c0db032dbf
Merge pull request #275 from efabless/gpio_control_block-fixes 
Gpio control block fixes
 2022-10-17 20:56:10 +02:00
Mohamed Shalan 3fbc52ecbf
Merge pull request #276 from efabless/caravel_redesign-digital_pll-fanout 
reharden!: digital_pll
 2022-10-17 20:50:01 +02:00
mo-hosni 2d147966b9 Update housekeeping views and openlane configuration 2022-10-17 11:37:24 -07:00
kareem e5d9788a43 reharden!: digital_pll 
~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys

!need to verify that the oscillator remains untouched
 2022-10-17 10:56:01 -07:00
kareem d241ca64c2 add substrateCut layer on top of gpio_logic_high in gpio_control_block 2022-10-17 10:25:04 -07:00
Marwan Abbas c524106fed
Merge pull request #263 from efabless/caravel_redesign-pdn-again 
update caravel pdn
 2022-10-17 16:12:01 +02:00
kareem d416d222b2 sync mag and lef with gds 2022-10-17 06:15:52 -07:00
kareem a8794dff4b reharden: caravel 
~ reharden with updated pdn
~ add stubs for non functional blocks
 2022-10-17 03:59:28 -07:00
kareem 394546731f update caravel pdn 
~ change pr boundary to origin to (0,0)
~ sync lef and mag with gds
 2022-10-17 03:51:21 -07:00
marwaneltoukhy 2d28c973ee added views for caravel with power routing 2022-10-16 19:08:56 -07:00
marwaneltoukhy 7ec1eeb010 Merge branch 'caravel_redesign' into caravel_redesign-top-level 2022-10-16 18:39:39 -07:00
Tim Edwards 69d353f65c Corrected the verilog and the layout for the caravan version of the 
signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
 2022-10-16 21:06:27 -04:00
kareem 2409207178 reharden: caravel 
~ add non functional blocks - like caravel_motto
 2022-10-16 15:44:27 -07:00
Tim Edwards f7e2dc80a6 Made a minor correction to the layout to remove an extra unused 
buffer.  This does not affect ongoing top-level routing work, but
is needed for LVS.
 2022-10-16 17:57:14 -04:00
kareem 704f19b6c7 reharden: caravel 
~ correct placement for spare_logic_block
~ add changes from buffering macro
 2022-10-16 12:56:41 -07:00
kareem 7ff92e121f Merge remote-tracking branch 'origin/fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 11:18:54 -07:00
Tim Edwards 48ae31205c Another change to the pin endpoint positions to make sure that they 
have at least 0.28um spacing to the next wire.  Not sure that this
is going to solve the router errors, though.
 2022-10-16 14:15:12 -04:00
kareem 2a3493ed65 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 10:03:54 -07:00
Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals 
being buffered pass through the buffer macros.  Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
 2022-10-16 12:49:44 -04:00
kareem b9a2e697d5 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 08:00:37 -07:00
Tim Edwards 589f351dcb Additional modification to move pins up into an uncongested area 
above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections.  Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
 2022-10-16 10:52:53 -04:00
kareem 38e78abfd5 Merge branch 'fix_top_buffers_again' into caravel_redesign-top-level 2022-10-16 07:24:15 -07:00
Tim Edwards 43b8f9d4fe Merge branch 'caravel_redesign' into fix_top_buffers_again 
Updating to the most recent caravel_redesign branch version.
 2022-10-16 10:05:36 -04:00
kareem aa2dfe9421 Merge branch 'fix_top_buffers_again' of github.com:efabless/caravel into fix_top_buffers_again 2022-10-16 07:01:55 -07:00
kareem fc0701003c reharden: caravel 
- based on second iteration of the buffer macro
- change config with updated placement of spare logic macros
and power routing cell
 2022-10-16 06:58:46 -07:00
Tim Edwards dcc3c56b83 Some additional corrections to the gpio_signal_buffering cells. 
Corrected one instance where a buffer had incorrectly been replaced
with a decap cell.  Moved the left-hand side in by 0.6um to clear
the chip_io connections on the left-hand side.  Corrected a small
DRC error in a route position at the bottom.
 2022-10-16 09:50:20 -04:00
kareem f5a8382395 Merge branch 'caravel_redesign' into fix_top_buffers_again 2022-10-16 05:55:23 -07:00
Marwan Abbas 6c6fa6b502
Merge pull request #255 from efabless/caravel_power_routing-sync-views 
caravel_power_routing updates
 2022-10-16 14:15:19 +02:00
kareem 914971d253 + add pr boundary for caravel_power_routing 
based on feedback from tim in order to generate a lef view
with a zero origin and avoid any hacks

+ add caravel_power_routing lef
+ sync caravel_power_routing gds and mag
 2022-10-16 04:41:29 -07:00
Marwan Abbas cb051054af
Merge pull request #254 from mo-hosni/hk_without_lables 
housekeeping without labels
 2022-10-16 13:38:02 +02:00
mo-hosni 3f0bddbcc6 update openlane views 2022-10-16 03:45:30 -07:00
mo-hosni 22dde425ac add mgmt_protect views and openlane files 2022-10-16 03:14:55 -07:00
kareem 507446e719 Merge branch 'caravel_redesign' into fix_top_buffers_again 2022-10-16 02:01:52 -07:00
Tim Edwards a77a45babe Adjustments to the top level buffering cells to do various things 
like avoid obstructions in the padframe and power routing, add
decap, and separate coupling wires to reduce capacitance.
 2022-10-15 17:35:17 -04:00
kareem 5d5d019ea1 Revert "add buff_flash_clkrst" 
This reverts commit 2675487322.
 2022-10-15 08:47:02 -07:00
Tim Edwards 3db846b119 Fixes issues with the GPIO signal buffering by applying a bounding 
box to the layout, so that LEF and DEF positions are correct.
 2022-10-15 10:31:35 -04:00
mo-hosni 2675487322 add buff_flash_clkrst 2022-10-15 06:38:42 -07:00
kareem 3e3bd111c1 ~ correct paths refereces in mag and maglef files from openlane 2022-10-15 04:06:07 -07:00
Marwan Abbas 316f2dbb58
Merge pull request #238 from mo-hosni/update_mgmt_protect 
Update mgmt protect
 2022-10-15 11:27:59 +02:00
mo-hosni 3361c8787d Add mgmt_protect views and openlane files 2022-10-15 01:46:22 -07:00
passant5 8c0e4f7403
Merge branch 'caravel_redesign' into add_top_level_buffers 2022-10-15 00:28:14 +02:00
Tim Edwards 1f5a158077 Essentially the same commit as the last one, but setting the metal 
3 horizontal bus width to 0.5um, as requested, rather than 0.6um.
 2022-10-14 16:36:42 -04:00
Tim Edwards 276580feb4 Updated the metal 3 horizontal power stripes on the mgmt_protect_hv 
layout to make them 0.6um (up from 0.3um wide).
 2022-10-14 16:28:07 -04:00
Tim Edwards 92e2f5e8a4 Added layout views (.mag, GDS, DEF, and LEF) for the caravan 
variant of the top level GPIO signal buffering (module
gpio_signal_buffering_alt).
 2022-10-14 16:06:11 -04:00
Tim Edwards aff5817f30 Rewrote the layout for mgmt_protect_hv after correcting the pins, 
which had not been correctly annotated for ports and so were
marked only as plain labels, causing issues when using the cell
as a macro inside mgmt_protect.
 2022-10-14 15:11:52 -04:00
mo-hosni 0e01725608 add housekeeping views 2022-10-14 09:26:34 -07:00
kareem aadfb57609 reharden: caravel_clocking 
~ align pdn with top level
~ move spefs and sdfs output corners to signoff/*/openlane-signoff
 2022-10-14 05:24:49 -07:00
Tim Edwards 46d44793e2 Added layout for the gpio_signal_buffering module, including GDS, 
LEF, DEF, and magic views.
 2022-10-13 21:59:10 -04:00
kareem 6452f14de0 reimplement caravel with latest blocks updates and a buffer macro 2022-10-13 13:34:47 -07:00
Marwan Abbas f7299933ee
Merge pull request #217 from mo-hosni/buff_flash_clkrst 
Buff flash clkrst
 2022-10-13 20:53:18 +02:00