20 Commits

Author	SHA1	Message	Date
M0stafaRady	a572a8ec14	add gpio_all_i_user test	2022-10-10 09:07:32 -07:00
M0stafaRady	00364eb092	Add gpio_all_o_user test	2022-10-09 07:53:25 -07:00
M0stafaRady	08229d6a9b	Add gpio_all_bidir test but it still not working yet	2022-10-09 05:08:12 -07:00
M0stafaRady	e94a8e0477	add test la test	2022-10-08 06:25:26 -07:00
M0stafaRady	f072e9cb2d	Add gpio_all_i_pd	2022-10-07 06:41:21 -07:00
M0stafaRady	7e407e1155	Add test hk_disable	2022-10-06 10:12:12 -07:00
M0stafaRady	28b453783f	Add clock redirect test	2022-10-06 09:20:06 -07:00
M0stafaRady	8e72d5e13e	Add test uart_loopback	2022-10-06 03:12:44 -07:00
M0stafaRady	8e21a2f722	Add test pll	2022-10-05 13:58:36 -07:00
M0stafaRady	4610f6b004	Add trial of test gpio_all_i_pu still not work	2022-10-05 08:22:51 -07:00
M0stafaRady	e2b345dcbb	Add new test user_pass_thru_rd	2022-10-04 10:55:53 -07:00
M0stafaRady	5e523bce5b	Add spi master temp created to simulate the silicon validation test and to be removed after	2022-10-04 10:46:34 -07:00
M0stafaRady	11330823b7	Add hk_regs_wr_wb_cpu test	2022-10-04 03:24:15 -07:00
M0stafaRady	37244a2514	add 3 regressions r_rtl , r_gl,r_sdf	2022-10-03 09:01:08 -07:00
M0stafaRady	e81416bb51	add new test mgmt_gpio_bidir	2022-10-03 08:56:46 -07:00
M0stafaRady	79f26f6b38	add new test spi_master_rd	2022-10-03 05:36:36 -07:00
M0stafaRady	de2f4a3707	Add bitbang_spi_i test	2022-10-02 08:38:00 -07:00
M0stafaRady	1c48f527b8	add bitbang_spi_o tests	2022-10-01 12:39:54 -07:00
M0stafaRady	18b4f36525	add test uart_rx	2022-10-01 02:23:47 -07:00
M0stafaRady	add4c5f6c8	Adding cocotb evironment with tests and scripts to run	2022-09-30 03:52:34 -07:00