manarabdelaty
83863fe16e
Add timing log for caravel
2021-12-01 19:28:33 +02:00
Tim Edwards
0f90c813ed
Added a missing route that was not completed in the previous layout
...
update. Also changed the defaults block types in the layout so that
they match the gate-level netlist. This does not change the behavior
after assembly but lets LVS run correctly on the layout prior to final
assembly.
2021-11-30 14:38:25 -05:00
Tim Edwards
e0a318d2bf
Fixed the GL verilog for caravel and caravan to add the two changes
...
just made to the RTL verilog and layout, to separate out hk_cyc_o
and to hook up the housekeeping user_clock input.
2021-11-30 12:31:07 -05:00
Tim Edwards
1035e8b469
Updated caravel and caravan layouts to reflect the simple change
...
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core. Also: Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
2021-11-30 10:05:43 -05:00
manarabdelaty
c4efcec989
[DATA] Update housekeeping views
2021-11-30 13:00:33 +02:00
Tim Edwards
4c0a2303b1
Modified the GL netlists to match the layout for the GPIO defaults
...
blocks; that is, there are special versions of the block for the
first 6 GPIO pins. That should allow the GL netlists to simulate,
although the end goal is to have the gen_gpio_defaults.py script
modify the GL netlists to exactly match the configuration, as is
done for the .mag layouts.
2021-11-29 20:17:11 -05:00
Tim Edwards
84c97b74b2
Corrected the instance names in the layout so that they once again
...
correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 19:57:33 -05:00
jeffdi
4fd86a58d2
testing make ship
2021-11-29 16:04:43 -08:00
jeffdi
257cb4587f
testing make ship
2021-11-29 15:05:08 -08:00
jeffdi
3cf04b3e39
Merge remote-tracking branch 'origin/main' into main
2021-11-29 14:11:28 -08:00
jeffdi
41e21d2186
testing make ship
2021-11-29 14:11:12 -08:00
Tim Edwards
960a839456
Removed the read-only GDS references from the mgmt_project_hv.mag
...
file, which shouldn't be there.
2021-11-29 16:33:51 -05:00
jeffdi
36185601b7
testing make ship
2021-11-29 13:07:36 -08:00
jeffdi
d20955a655
testing make ship
2021-11-29 13:03:02 -08:00
Tim Edwards
cd4a052344
Made the same change to caravan as was made to caravel in the
...
last commit.
2021-11-29 14:27:02 -05:00
Tim Edwards
4dac106297
This (late and invasive) change modifies the housekeeping block to
...
add a separate signal for the houskeeping wb_cyc_i wishbone signal,
instead of combining it with the user project's wb_cyc_i. This
change makes it compatible with the LiteX implementation of the
wishbone bus.
2021-11-29 14:23:30 -05:00
manarabdelaty
d033d2e62d
[DATA] Add spef/sdf views
2021-11-28 15:28:59 +02:00
manarabdelaty
96803bf6b2
Merge branch 'main' of https://github.com/efabless/caravel_openframe into main
2021-11-28 15:06:38 +02:00
manarabdelaty
d4e97b91ed
Update Makefile to generate sdf file
2021-11-28 15:06:18 +02:00
jeffdi
42e2ea42d6
testing make ship
2021-11-27 16:21:01 -08:00
Tim Edwards
e2ee74c591
Changed "simple_por" in both caravel and caravan to be an abstract
...
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
2021-11-27 11:51:30 -05:00
Tim Edwards
f67f7b6daf
Corrected bad paths on two layouts in mag/ and most of the layouts
...
in maglef/, all of which were erroneously pointing to paths in
either OpenLane or the user's home directory path.
2021-11-26 20:00:47 -05:00
jeffdi
c820dfdb40
testing make ship
2021-11-26 16:29:57 -08:00
jeffdi
91b94ad919
test gen_gpio_defaults.py
2021-11-26 15:32:13 -08:00
jeffdi
fd81e0814b
test gen_gpio_defaults.py
2021-11-26 15:28:03 -08:00
jeffdi
b3320b7500
test gen_gpio_defaults.py
2021-11-26 14:04:00 -08:00
jeffdi
2ce03a196c
test gen_gpio_defaults.py
2021-11-26 14:03:03 -08:00
jeffdi
2bd7c40946
test gen_gpio_defaults.py
2021-11-26 14:01:12 -08:00
jeffdi
f996157088
test gen_gpio_defaults.py
2021-11-26 13:57:18 -08:00
jeffdi
f5f62923ff
Merge remote-tracking branch 'origin/main' into main
2021-11-25 09:59:22 -08:00
jeffdi
54a2f5d869
updated Makefile for update_mcw
2021-11-25 09:58:04 -08:00
manarabdelaty
299828169c
Update RCX target to extract caravel top level
2021-11-25 18:49:02 +02:00
manarabdelaty
8b1c5df909
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 15:23:01 +02:00
manarabdelaty
05278ec738
[DATA] Update HK views (timing clean)
2021-11-25 12:54:22 +02:00
Tim Edwards
fe21089505
Updated caravan with the same addition of four spare logic blocks
...
as was made to caravel.
2021-11-24 17:10:05 -05:00
Tim Edwards
be98da0fe6
Added spare logic block to caravel layout and verilog GL, wired
...
it to the power supply, and checked top-level LVS.
2021-11-24 16:50:22 -05:00
manarabdelaty
b60a4c1191
Merge branch 'main' of https://github.com/efabless/caravel_openframe into main
2021-11-24 20:36:56 +02:00
manarabdelaty
83e150bf25
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00
jeffdi
ec86ebb2df
added install_mcw make target
2021-11-24 09:23:58 -08:00
Tim Edwards
543fee18e3
Revised the spare logic block to make sure that all inputs are
...
reachable from pins on the boundary once it's synthesized.
2021-11-24 09:34:52 -05:00
Tim Edwards
2b156997cb
Added a new module with "spare logic" for metal mask fixes.
2021-11-24 09:23:22 -05:00
Tim Edwards
9b1a18a15e
Finished drawing all of the analog connections to meet cleanly at
...
the user analog project boundary.
2021-11-23 17:32:52 -05:00
Tim Edwards
0114df40ae
Added additional power routing from the sides of Caravel to the
...
user project power ring. If that is incompatible with user
projects and/or the XOR check, then this commit might need to be
reverted.
2021-11-23 16:49:23 -05:00
Tim Edwards
0ba8884b00
Added a motto for each chip. Just because.
2021-11-23 15:19:41 -05:00
Tim Edwards
1ff48245e8
Pushing final layout of Caravan, now LVS clean.
2021-11-23 14:06:14 -05:00
Tim Edwards
5d3f2a26f4
Corrected the Caravel layout and the Caravel and Caravan GL netlists
...
to resolve the problem with the typo that caused the propagated
GPIO serial load, reset, and clock signals to get scrambled on the
user2 side. Caravel is now LVS clean again (Caravan needs layout
work).
2021-11-23 11:47:17 -05:00
Tim Edwards
08a2c90940
Made updates to correct LVS errors in caravan. Found one major error in the RTL
...
verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to
correct this; still need to correct the layouts. The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing. Will route this by hand.
2021-11-22 22:35:52 -05:00
Tim Edwards
e86831b188
Final edits to make caravel LVS clean.
2021-11-22 16:51:35 -05:00
manarabdelaty
aeffe4756a
[DATA] Add caravan layout
2021-11-22 23:10:25 +02:00
manarabdelaty
38f64d08a3
[DATA] Add user_analog_project_wrapper and chip_io_alt gds/lef views
2021-11-22 23:08:25 +02:00