mirror of https://github.com/efabless/caravel.git
[DATA] Add spef/sdf views
This commit is contained in:
manarabdelaty
parent
96803bf6b2
commit
d033d2e62d
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@ -0,0 +1,34 @@
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(DELAYFILE
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(SDFVERSION "3.0")
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(DESIGN "gpio_defaults_block")
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(DATE "Sun Nov 28 13:23:59 2021")
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(VENDOR "Parallax")
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(PROGRAM "STA")
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(VERSION "2.3.0")
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(DIVIDER /)
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(VOLTAGE 1.800::1.800)
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(PROCESS "1.000::1.000")
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(TEMPERATURE 25.000::25.000)
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(TIMESCALE 1ns)
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(CELL
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(CELLTYPE "gpio_defaults_block")
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(INSTANCE)
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(DELAY
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(ABSOLUTE
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(INTERCONNECT gpio_default_value\[0\]/LO gpio_defaults[0] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[10\]/HI gpio_defaults[10] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[11\]/LO gpio_defaults[11] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[12\]/LO gpio_defaults[12] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[1\]/HI gpio_defaults[1] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[2\]/LO gpio_defaults[2] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[3\]/LO gpio_defaults[3] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[4\]/LO gpio_defaults[4] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[5\]/LO gpio_defaults[5] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[6\]/LO gpio_defaults[6] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[7\]/LO gpio_defaults[7] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[8\]/LO gpio_defaults[8] (0.000::0.000))
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(INTERCONNECT gpio_default_value\[9\]/LO gpio_defaults[9] (0.000::0.000))
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)
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)
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)
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)
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@ -0,0 +1,22 @@
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(DELAYFILE
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(SDFVERSION "3.0")
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(DESIGN "gpio_logic_high")
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(DATE "Sun Nov 28 13:23:43 2021")
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(VENDOR "Parallax")
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(PROGRAM "STA")
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(VERSION "2.3.0")
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(DIVIDER /)
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(VOLTAGE 1.800::1.800)
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(PROCESS "1.000::1.000")
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(TEMPERATURE 25.000::25.000)
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(TIMESCALE 1ns)
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(CELL
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(CELLTYPE "gpio_logic_high")
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(INSTANCE)
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(DELAY
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(ABSOLUTE
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(INTERCONNECT gpio_logic_high/HI gpio_logic1 (0.000::0.000))
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)
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)
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)
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)
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@ -0,0 +1,22 @@
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(DELAYFILE
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(SDFVERSION "3.0")
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(DESIGN "mprj2_logic_high")
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(DATE "Sun Nov 28 13:25:10 2021")
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(VENDOR "Parallax")
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(PROGRAM "STA")
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(VERSION "2.3.0")
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(DIVIDER /)
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(VOLTAGE 1.800::1.800)
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(PROCESS "1.000::1.000")
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(TEMPERATURE 25.000::25.000)
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(TIMESCALE 1ns)
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(CELL
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(CELLTYPE "mprj2_logic_high")
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(INSTANCE)
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(DELAY
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(ABSOLUTE
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(INTERCONNECT inst/HI HI (0.000::0.000))
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)
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)
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)
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)
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@ -0,0 +1,484 @@
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(DELAYFILE
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(SDFVERSION "3.0")
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(DESIGN "mprj_logic_high")
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(DATE "Sun Nov 28 13:24:55 2021")
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(VENDOR "Parallax")
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(PROGRAM "STA")
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(VERSION "2.3.0")
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(DIVIDER /)
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(VOLTAGE 1.800::1.800)
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(PROCESS "1.000::1.000")
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(TEMPERATURE 25.000::25.000)
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(TIMESCALE 1ns)
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(CELL
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(CELLTYPE "mprj_logic_high")
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(INSTANCE)
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(DELAY
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(ABSOLUTE
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(INTERCONNECT insts\[0\]/HI HI[0] (0.000::0.000))
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(INTERCONNECT insts\[100\]/HI HI[100] (0.000::0.000))
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(INTERCONNECT insts\[101\]/HI HI[101] (0.000::0.000))
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(INTERCONNECT insts\[102\]/HI HI[102] (0.000::0.000))
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(INTERCONNECT insts\[103\]/HI HI[103] (0.000::0.000))
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(INTERCONNECT insts\[104\]/HI HI[104] (0.000::0.000))
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(INTERCONNECT insts\[105\]/HI HI[105] (0.000::0.000))
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(INTERCONNECT insts\[106\]/HI HI[106] (0.000::0.000))
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(INTERCONNECT insts\[107\]/HI HI[107] (0.000::0.000))
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(INTERCONNECT insts\[108\]/HI HI[108] (0.000::0.000))
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(INTERCONNECT insts\[109\]/HI HI[109] (0.000::0.000))
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(INTERCONNECT insts\[10\]/HI HI[10] (0.000::0.000))
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(INTERCONNECT insts\[110\]/HI HI[110] (0.000::0.000))
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(INTERCONNECT insts\[111\]/HI HI[111] (0.000::0.000))
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(INTERCONNECT insts\[112\]/HI HI[112] (0.000::0.000))
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(INTERCONNECT insts\[113\]/HI HI[113] (0.000::0.000))
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(INTERCONNECT insts\[114\]/HI HI[114] (0.000::0.000))
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(INTERCONNECT insts\[115\]/HI HI[115] (0.000::0.000))
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(INTERCONNECT insts\[116\]/HI HI[116] (0.000::0.000))
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(INTERCONNECT insts\[117\]/HI HI[117] (0.000::0.000))
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(INTERCONNECT insts\[118\]/HI HI[118] (0.000::0.000))
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(INTERCONNECT insts\[119\]/HI HI[119] (0.000::0.000))
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(INTERCONNECT insts\[11\]/HI HI[11] (0.000::0.000))
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(INTERCONNECT insts\[120\]/HI HI[120] (0.000::0.000))
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(INTERCONNECT insts\[121\]/HI HI[121] (0.000::0.000))
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(INTERCONNECT insts\[122\]/HI HI[122] (0.000::0.000))
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(INTERCONNECT insts\[123\]/HI HI[123] (0.000::0.000))
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(INTERCONNECT insts\[124\]/HI HI[124] (0.000::0.000))
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(INTERCONNECT insts\[125\]/HI HI[125] (0.000::0.000))
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(INTERCONNECT insts\[126\]/HI HI[126] (0.000::0.000))
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(INTERCONNECT insts\[127\]/HI HI[127] (0.000::0.000))
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(INTERCONNECT insts\[128\]/HI HI[128] (0.000::0.000))
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(INTERCONNECT insts\[129\]/HI HI[129] (0.000::0.000))
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(INTERCONNECT insts\[12\]/HI HI[12] (0.000::0.000))
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(INTERCONNECT insts\[130\]/HI HI[130] (0.000::0.000))
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(INTERCONNECT insts\[131\]/HI HI[131] (0.000::0.000))
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(INTERCONNECT insts\[132\]/HI HI[132] (0.000::0.000))
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(INTERCONNECT insts\[133\]/HI HI[133] (0.000::0.000))
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(INTERCONNECT insts\[134\]/HI HI[134] (0.000::0.000))
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(INTERCONNECT insts\[135\]/HI HI[135] (0.000::0.000))
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(INTERCONNECT insts\[136\]/HI HI[136] (0.000::0.000))
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(INTERCONNECT insts\[137\]/HI HI[137] (0.000::0.000))
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(INTERCONNECT insts\[138\]/HI HI[138] (0.000::0.000))
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(INTERCONNECT insts\[139\]/HI HI[139] (0.000::0.000))
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(INTERCONNECT insts\[13\]/HI HI[13] (0.000::0.000))
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(INTERCONNECT insts\[140\]/HI HI[140] (0.000::0.000))
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(INTERCONNECT insts\[141\]/HI HI[141] (0.000::0.000))
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(INTERCONNECT insts\[142\]/HI HI[142] (0.000::0.000))
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(INTERCONNECT insts\[143\]/HI HI[143] (0.000::0.000))
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(INTERCONNECT insts\[144\]/HI HI[144] (0.000::0.000))
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(INTERCONNECT insts\[145\]/HI HI[145] (0.000::0.000))
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(INTERCONNECT insts\[146\]/HI HI[146] (0.000::0.000))
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(INTERCONNECT insts\[147\]/HI HI[147] (0.000::0.000))
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(INTERCONNECT insts\[148\]/HI HI[148] (0.000::0.000))
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(INTERCONNECT insts\[149\]/HI HI[149] (0.000::0.000))
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(INTERCONNECT insts\[14\]/HI HI[14] (0.000::0.000))
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(INTERCONNECT insts\[150\]/HI HI[150] (0.000::0.000))
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(INTERCONNECT insts\[151\]/HI HI[151] (0.000::0.000))
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(INTERCONNECT insts\[152\]/HI HI[152] (0.000::0.000))
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(INTERCONNECT insts\[153\]/HI HI[153] (0.000::0.000))
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(INTERCONNECT insts\[154\]/HI HI[154] (0.000::0.000))
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(INTERCONNECT insts\[155\]/HI HI[155] (0.000::0.000))
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(INTERCONNECT insts\[156\]/HI HI[156] (0.000::0.000))
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(INTERCONNECT insts\[157\]/HI HI[157] (0.000::0.000))
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(INTERCONNECT insts\[158\]/HI HI[158] (0.000::0.000))
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(INTERCONNECT insts\[159\]/HI HI[159] (0.000::0.000))
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(INTERCONNECT insts\[15\]/HI HI[15] (0.000::0.000))
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(INTERCONNECT insts\[160\]/HI HI[160] (0.000::0.000))
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(INTERCONNECT insts\[161\]/HI HI[161] (0.000::0.000))
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(INTERCONNECT insts\[162\]/HI HI[162] (0.000::0.000))
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(INTERCONNECT insts\[163\]/HI HI[163] (0.000::0.000))
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(INTERCONNECT insts\[164\]/HI HI[164] (0.000::0.000))
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(INTERCONNECT insts\[165\]/HI HI[165] (0.000::0.000))
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(INTERCONNECT insts\[166\]/HI HI[166] (0.000::0.000))
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(INTERCONNECT insts\[167\]/HI HI[167] (0.000::0.000))
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(INTERCONNECT insts\[168\]/HI HI[168] (0.000::0.000))
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(INTERCONNECT insts\[169\]/HI HI[169] (0.000::0.000))
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(INTERCONNECT insts\[16\]/HI HI[16] (0.000::0.000))
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(INTERCONNECT insts\[170\]/HI HI[170] (0.000::0.000))
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(INTERCONNECT insts\[171\]/HI HI[171] (0.000::0.000))
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(INTERCONNECT insts\[172\]/HI HI[172] (0.000::0.000))
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(INTERCONNECT insts\[173\]/HI HI[173] (0.000::0.000))
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(INTERCONNECT insts\[174\]/HI HI[174] (0.000::0.000))
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(INTERCONNECT insts\[175\]/HI HI[175] (0.000::0.000))
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(INTERCONNECT insts\[176\]/HI HI[176] (0.000::0.000))
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(INTERCONNECT insts\[177\]/HI HI[177] (0.000::0.000))
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(INTERCONNECT insts\[178\]/HI HI[178] (0.000::0.000))
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(INTERCONNECT insts\[179\]/HI HI[179] (0.000::0.000))
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(INTERCONNECT insts\[17\]/HI HI[17] (0.000::0.000))
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(INTERCONNECT insts\[180\]/HI HI[180] (0.000::0.000))
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(INTERCONNECT insts\[181\]/HI HI[181] (0.000::0.000))
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(INTERCONNECT insts\[182\]/HI HI[182] (0.000::0.000))
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(INTERCONNECT insts\[183\]/HI HI[183] (0.000::0.000))
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(INTERCONNECT insts\[184\]/HI HI[184] (0.000::0.000))
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(INTERCONNECT insts\[185\]/HI HI[185] (0.000::0.000))
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(INTERCONNECT insts\[186\]/HI HI[186] (0.000::0.000))
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(INTERCONNECT insts\[187\]/HI HI[187] (0.000::0.000))
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(INTERCONNECT insts\[188\]/HI HI[188] (0.000::0.000))
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(INTERCONNECT insts\[189\]/HI HI[189] (0.000::0.000))
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(INTERCONNECT insts\[18\]/HI HI[18] (0.000::0.000))
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(INTERCONNECT insts\[190\]/HI HI[190] (0.000::0.000))
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(INTERCONNECT insts\[191\]/HI HI[191] (0.000::0.000))
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(INTERCONNECT insts\[192\]/HI HI[192] (0.000::0.000))
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(INTERCONNECT insts\[193\]/HI HI[193] (0.000::0.000))
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(INTERCONNECT insts\[194\]/HI HI[194] (0.000::0.000))
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(INTERCONNECT insts\[195\]/HI HI[195] (0.000::0.000))
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(INTERCONNECT insts\[196\]/HI HI[196] (0.000::0.000))
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(INTERCONNECT insts\[197\]/HI HI[197] (0.000::0.000))
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(INTERCONNECT insts\[198\]/HI HI[198] (0.000::0.000))
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(INTERCONNECT insts\[199\]/HI HI[199] (0.000::0.000))
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(INTERCONNECT insts\[19\]/HI HI[19] (0.000::0.000))
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(INTERCONNECT insts\[1\]/HI HI[1] (0.000::0.000))
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(INTERCONNECT insts\[200\]/HI HI[200] (0.000::0.000))
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(INTERCONNECT insts\[201\]/HI HI[201] (0.000::0.000))
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(INTERCONNECT insts\[202\]/HI HI[202] (0.000::0.000))
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(INTERCONNECT insts\[203\]/HI HI[203] (0.000::0.000))
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(INTERCONNECT insts\[204\]/HI HI[204] (0.000::0.000))
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(INTERCONNECT insts\[205\]/HI HI[205] (0.000::0.000))
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(INTERCONNECT insts\[206\]/HI HI[206] (0.000::0.000))
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(INTERCONNECT insts\[207\]/HI HI[207] (0.000::0.000))
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(INTERCONNECT insts\[208\]/HI HI[208] (0.000::0.000))
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(INTERCONNECT insts\[209\]/HI HI[209] (0.000::0.000))
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(INTERCONNECT insts\[20\]/HI HI[20] (0.000::0.000))
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(INTERCONNECT insts\[210\]/HI HI[210] (0.000::0.000))
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(INTERCONNECT insts\[211\]/HI HI[211] (0.000::0.000))
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(INTERCONNECT insts\[212\]/HI HI[212] (0.000::0.000))
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(INTERCONNECT insts\[213\]/HI HI[213] (0.000::0.000))
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(INTERCONNECT insts\[214\]/HI HI[214] (0.000::0.000))
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(INTERCONNECT insts\[215\]/HI HI[215] (0.000::0.000))
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(INTERCONNECT insts\[216\]/HI HI[216] (0.000::0.000))
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(INTERCONNECT insts\[217\]/HI HI[217] (0.000::0.000))
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(INTERCONNECT insts\[218\]/HI HI[218] (0.000::0.000))
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(INTERCONNECT insts\[219\]/HI HI[219] (0.000::0.000))
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(INTERCONNECT insts\[21\]/HI HI[21] (0.000::0.000))
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(INTERCONNECT insts\[220\]/HI HI[220] (0.000::0.000))
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(INTERCONNECT insts\[221\]/HI HI[221] (0.000::0.000))
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(INTERCONNECT insts\[222\]/HI HI[222] (0.000::0.000))
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(INTERCONNECT insts\[223\]/HI HI[223] (0.000::0.000))
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(INTERCONNECT insts\[224\]/HI HI[224] (0.000::0.000))
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(INTERCONNECT insts\[225\]/HI HI[225] (0.000::0.000))
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(INTERCONNECT insts\[226\]/HI HI[226] (0.000::0.000))
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(INTERCONNECT insts\[227\]/HI HI[227] (0.000::0.000))
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(INTERCONNECT insts\[228\]/HI HI[228] (0.000::0.000))
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(INTERCONNECT insts\[229\]/HI HI[229] (0.000::0.000))
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(INTERCONNECT insts\[22\]/HI HI[22] (0.000::0.000))
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(INTERCONNECT insts\[230\]/HI HI[230] (0.000::0.000))
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(INTERCONNECT insts\[231\]/HI HI[231] (0.000::0.000))
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(INTERCONNECT insts\[232\]/HI HI[232] (0.000::0.000))
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(INTERCONNECT insts\[233\]/HI HI[233] (0.000::0.000))
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(INTERCONNECT insts\[234\]/HI HI[234] (0.000::0.000))
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(INTERCONNECT insts\[235\]/HI HI[235] (0.000::0.000))
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(INTERCONNECT insts\[236\]/HI HI[236] (0.000::0.000))
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(INTERCONNECT insts\[237\]/HI HI[237] (0.000::0.000))
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(INTERCONNECT insts\[238\]/HI HI[238] (0.000::0.000))
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(INTERCONNECT insts\[239\]/HI HI[239] (0.000::0.000))
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(INTERCONNECT insts\[23\]/HI HI[23] (0.000::0.000))
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(INTERCONNECT insts\[240\]/HI HI[240] (0.000::0.000))
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(INTERCONNECT insts\[241\]/HI HI[241] (0.000::0.000))
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(INTERCONNECT insts\[242\]/HI HI[242] (0.000::0.000))
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(INTERCONNECT insts\[243\]/HI HI[243] (0.000::0.000))
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(INTERCONNECT insts\[244\]/HI HI[244] (0.000::0.000))
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(INTERCONNECT insts\[245\]/HI HI[245] (0.000::0.000))
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(INTERCONNECT insts\[246\]/HI HI[246] (0.000::0.000))
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(INTERCONNECT insts\[247\]/HI HI[247] (0.000::0.000))
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(INTERCONNECT insts\[248\]/HI HI[248] (0.000::0.000))
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(INTERCONNECT insts\[249\]/HI HI[249] (0.000::0.000))
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(INTERCONNECT insts\[24\]/HI HI[24] (0.000::0.000))
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(INTERCONNECT insts\[250\]/HI HI[250] (0.000::0.000))
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(INTERCONNECT insts\[251\]/HI HI[251] (0.000::0.000))
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(INTERCONNECT insts\[252\]/HI HI[252] (0.000::0.000))
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(INTERCONNECT insts\[253\]/HI HI[253] (0.000::0.000))
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(INTERCONNECT insts\[254\]/HI HI[254] (0.000::0.000))
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(INTERCONNECT insts\[255\]/HI HI[255] (0.000::0.000))
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(INTERCONNECT insts\[256\]/HI HI[256] (0.000::0.000))
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(INTERCONNECT insts\[257\]/HI HI[257] (0.000::0.000))
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(INTERCONNECT insts\[258\]/HI HI[258] (0.000::0.000))
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(INTERCONNECT insts\[259\]/HI HI[259] (0.000::0.000))
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(INTERCONNECT insts\[25\]/HI HI[25] (0.000::0.000))
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(INTERCONNECT insts\[260\]/HI HI[260] (0.000::0.000))
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(INTERCONNECT insts\[261\]/HI HI[261] (0.000::0.000))
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(INTERCONNECT insts\[262\]/HI HI[262] (0.000::0.000))
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(INTERCONNECT insts\[263\]/HI HI[263] (0.000::0.000))
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(INTERCONNECT insts\[264\]/HI HI[264] (0.000::0.000))
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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(INTERCONNECT insts\[70\]/HI HI[70] (0.000::0.000))
|
||||
(INTERCONNECT insts\[71\]/HI HI[71] (0.000::0.000))
|
||||
(INTERCONNECT insts\[72\]/HI HI[72] (0.000::0.000))
|
||||
(INTERCONNECT insts\[73\]/HI HI[73] (0.000::0.000))
|
||||
(INTERCONNECT insts\[74\]/HI HI[74] (0.000::0.000))
|
||||
(INTERCONNECT insts\[75\]/HI HI[75] (0.000::0.000))
|
||||
(INTERCONNECT insts\[76\]/HI HI[76] (0.000::0.000))
|
||||
(INTERCONNECT insts\[77\]/HI HI[77] (0.000::0.000))
|
||||
(INTERCONNECT insts\[78\]/HI HI[78] (0.000::0.000))
|
||||
(INTERCONNECT insts\[79\]/HI HI[79] (0.000::0.000))
|
||||
(INTERCONNECT insts\[7\]/HI HI[7] (0.000::0.000))
|
||||
(INTERCONNECT insts\[80\]/HI HI[80] (0.000::0.000))
|
||||
(INTERCONNECT insts\[81\]/HI HI[81] (0.000::0.000))
|
||||
(INTERCONNECT insts\[82\]/HI HI[82] (0.000::0.000))
|
||||
(INTERCONNECT insts\[83\]/HI HI[83] (0.000::0.000))
|
||||
(INTERCONNECT insts\[84\]/HI HI[84] (0.000::0.000))
|
||||
(INTERCONNECT insts\[85\]/HI HI[85] (0.000::0.000))
|
||||
(INTERCONNECT insts\[86\]/HI HI[86] (0.000::0.000))
|
||||
(INTERCONNECT insts\[87\]/HI HI[87] (0.000::0.000))
|
||||
(INTERCONNECT insts\[88\]/HI HI[88] (0.000::0.000))
|
||||
(INTERCONNECT insts\[89\]/HI HI[89] (0.000::0.000))
|
||||
(INTERCONNECT insts\[8\]/HI HI[8] (0.000::0.000))
|
||||
(INTERCONNECT insts\[90\]/HI HI[90] (0.000::0.000))
|
||||
(INTERCONNECT insts\[91\]/HI HI[91] (0.000::0.000))
|
||||
(INTERCONNECT insts\[92\]/HI HI[92] (0.000::0.000))
|
||||
(INTERCONNECT insts\[93\]/HI HI[93] (0.000::0.000))
|
||||
(INTERCONNECT insts\[94\]/HI HI[94] (0.000::0.000))
|
||||
(INTERCONNECT insts\[95\]/HI HI[95] (0.000::0.000))
|
||||
(INTERCONNECT insts\[96\]/HI HI[96] (0.000::0.000))
|
||||
(INTERCONNECT insts\[97\]/HI HI[97] (0.000::0.000))
|
||||
(INTERCONNECT insts\[98\]/HI HI[98] (0.000::0.000))
|
||||
(INTERCONNECT insts\[99\]/HI HI[99] (0.000::0.000))
|
||||
(INTERCONNECT insts\[9\]/HI HI[9] (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "spare_logic_block")
|
||||
(DATE "Sun Nov 28 13:27:22 2021")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.0")
|
||||
(DIVIDER /)
|
||||
(VOLTAGE 1.800::1.800)
|
||||
(PROCESS "1.000::1.000")
|
||||
(TEMPERATURE 25.000::25.000)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "spare_logic_block")
|
||||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT spare_logic_biginv/Y spare_xib (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\]/LO spare_xz[0] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\]/LO spare_logic_inv\[0\]/A (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\]/LO spare_xz[10] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\]/LO spare_logic_nor\[1\]/A (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\]/LO spare_xz[11] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\]/LO spare_logic_nor\[0\]/B (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\]/LO spare_xz[12] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\]/LO spare_logic_nor\[1\]/B (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\]/LO spare_xz[13] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\]/LO spare_logic_mux\[0\]/A0 (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\]/LO spare_xz[14] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\]/LO spare_logic_mux\[1\]/A0 (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\]/LO spare_xz[15] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\]/LO spare_logic_mux\[0\]/A1 (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\]/LO spare_xz[16] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\]/LO spare_logic_mux\[1\]/A1 (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\]/LO spare_xz[17] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\]/LO spare_logic_mux\[0\]/S (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\]/LO spare_xz[18] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\]/LO spare_logic_mux\[1\]/S (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\]/LO spare_xz[19] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\]/LO spare_logic_flop\[0\]/D (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\]/LO spare_xz[1] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\]/LO spare_logic_inv\[1\]/A (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\]/LO spare_xz[20] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\]/LO spare_logic_flop\[1\]/D (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\]/LO spare_xz[21] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\]/LO spare_logic_flop\[0\]/CLK (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\]/LO spare_xz[22] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\]/LO spare_logic_flop\[1\]/CLK (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\]/LO spare_xz[23] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\]/LO spare_logic_flop\[0\]/SET_B (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\]/LO spare_xz[24] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\]/LO spare_logic_flop\[1\]/SET_B (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\]/LO spare_xz[25] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\]/LO spare_logic_flop\[0\]/RESET_B (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\]/LO spare_xz[26] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\]/LO spare_logic_flop\[1\]/RESET_B (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\]/LO spare_xz[2] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\]/LO spare_logic_inv\[2\]/A (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\]/LO spare_xz[3] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\]/LO spare_logic_inv\[3\]/A (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\]/LO spare_xz[4] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\]/LO spare_logic_biginv/A (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\]/LO spare_xz[5] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\]/LO spare_logic_nand\[0\]/A (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\]/LO spare_xz[6] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\]/LO spare_logic_nand\[1\]/A (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\]/LO spare_xz[7] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\]/LO spare_logic_nand\[0\]/B (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\]/LO spare_xz[8] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\]/LO spare_logic_nand\[1\]/B (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\]/LO spare_xz[9] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\]/LO spare_logic_nor\[0\]/A (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\]/Q spare_xfq[0] (0.001::0.001))
|
||||
(INTERCONNECT spare_logic_flop\[0\]/Q_N spare_xfqn[0] (0.001::0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\]/Q spare_xfq[1] (0.001::0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\]/Q_N spare_xfqn[1] (0.001::0.001))
|
||||
(INTERCONNECT spare_logic_inv\[0\]/Y spare_xi[0] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_inv\[1\]/Y spare_xi[1] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_inv\[2\]/Y spare_xi[2] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_inv\[3\]/Y spare_xi[3] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_mux\[0\]/X spare_xmx[0] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_mux\[1\]/X spare_xmx[1] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_nand\[0\]/Y spare_xna[0] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_nand\[1\]/Y spare_xna[1] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_nor\[0\]/Y spare_xno[0] (0.000::0.000))
|
||||
(INTERCONNECT spare_logic_nor\[1\]/Y spare_xno[1] (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_8")
|
||||
(INSTANCE spare_logic_biginv)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RESET_B Q_N (0.000::0.000))
|
||||
(IOPATH RESET_B Q () (0.000::0.000))
|
||||
(IOPATH SET_B Q_N () (0.000::0.000))
|
||||
(IOPATH SET_B Q (0.000::0.000))
|
||||
(IOPATH CLK Q_N (0.000::0.000))
|
||||
(IOPATH CLK Q (0.000::0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000::0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000::0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000::0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000::0.000))
|
||||
(HOLD D (posedge CLK) (0.000::0.000))
|
||||
(SETUP D (posedge CLK) (0.000::0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RESET_B Q_N (0.000::0.000))
|
||||
(IOPATH RESET_B Q () (0.000::0.000))
|
||||
(IOPATH SET_B Q_N () (0.000::0.000))
|
||||
(IOPATH SET_B Q (0.000::0.000))
|
||||
(IOPATH CLK Q_N (0.000::0.000))
|
||||
(IOPATH CLK Q (0.000::0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000::0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000::0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000::0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000::0.000))
|
||||
(HOLD D (posedge CLK) (0.000::0.000))
|
||||
(SETUP D (posedge CLK) (0.000::0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000::0.000))
|
||||
(IOPATH A1 X (0.000::0.000))
|
||||
(IOPATH S X (0.000::0.000))
|
||||
(IOPATH S X (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000::0.000))
|
||||
(IOPATH A1 X (0.000::0.000))
|
||||
(IOPATH S X (0.000::0.000))
|
||||
(IOPATH S X (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000::0.000))
|
||||
(IOPATH B Y (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000::0.000))
|
||||
(IOPATH B Y (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000::0.000))
|
||||
(IOPATH B Y (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000::0.000))
|
||||
(IOPATH B Y (0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
set ::env(IO_PCT) "0.2"
|
||||
set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_1"
|
||||
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
|
||||
set ::env(SYNTH_MAX_FANOUT) "5"
|
||||
set ::env(SYNTH_CAP_LOAD) "33.442"
|
||||
set ::env(SYNTH_TIMING_DERATE) 0.05
|
||||
set ::env(SYNTH_CLOCK_UNCERTAINITY) 0.25
|
||||
set ::env(SYNTH_CLOCK_TRANSITION) 0.15
|
||||
|
||||
## MASTER CLOCKS
|
||||
create_clock [get_ports {"clock"} ] -name "clock" -period 25
|
||||
create_clock -name __VIRTUAL_CLK__ -period 25
|
||||
|
||||
## INPUT/OUTPUT DELAYS
|
||||
set input_delay_value 1
|
||||
set output_delay_value [expr 25 * $::env(IO_PCT)]
|
||||
puts "\[INFO\]: Setting output delay to: $output_delay_value"
|
||||
puts "\[INFO\]: Setting input delay to: $input_delay_value"
|
||||
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {gpio}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[0]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[1]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[2]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[3]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[4]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[5]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[6]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[7]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[8]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[9]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[10]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[11]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[12]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[13]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[14]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[15]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[16]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[17]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[18]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[19]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[20]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[21]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[22]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[23]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[25]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[26]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[27]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[28]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[33]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[34]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[35]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[36]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[37]}]
|
||||
|
||||
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_csb}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_clk}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io1}]
|
||||
|
||||
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
|
||||
|
||||
# TODO set this as parameter
|
||||
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
|
||||
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
|
||||
puts "\[INFO\]: Setting load to: $cap_load"
|
||||
set_load $cap_load [all_outputs]
|
||||
|
||||
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
|
||||
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
|
||||
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
|
||||
|
||||
puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
|
||||
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {clock}]
|
||||
|
||||
puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
|
||||
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clock}]
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,82 @@
|
|||
set ::env(IO_PCT) "0.2"
|
||||
set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_1"
|
||||
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
|
||||
set ::env(SYNTH_MAX_FANOUT) "5"
|
||||
set ::env(SYNTH_CAP_LOAD) "33.442"
|
||||
set ::env(SYNTH_TIMING_DERATE) 0.05
|
||||
set ::env(SYNTH_CLOCK_UNCERTAINITY) 0.25
|
||||
set ::env(SYNTH_CLOCK_TRANSITION) 0.15
|
||||
|
||||
## MASTER CLOCKS
|
||||
create_clock [get_ports {"clock"} ] -name "clock" -period 25
|
||||
create_clock -name __VIRTUAL_CLK__ -period 25
|
||||
|
||||
## INPUT/OUTPUT DELAYS
|
||||
set input_delay_value 1
|
||||
set output_delay_value [expr 25 * $::env(IO_PCT)]
|
||||
puts "\[INFO\]: Setting output delay to: $output_delay_value"
|
||||
puts "\[INFO\]: Setting input delay to: $input_delay_value"
|
||||
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {gpio}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[0]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[1]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[2]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[3]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[4]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[5]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[6]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[7]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[8]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[9]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[10]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[11]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[12]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[13]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[14]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[15]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[16]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[17]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[18]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[19]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[20]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[21]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[22]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[23]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[25]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[26]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[27]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[28]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[33]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[34]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[35]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[36]}]
|
||||
set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[37]}]
|
||||
|
||||
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_csb}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_clk}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}]
|
||||
set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io1}]
|
||||
|
||||
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
|
||||
|
||||
# TODO set this as parameter
|
||||
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
|
||||
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
|
||||
puts "\[INFO\]: Setting load to: $cap_load"
|
||||
set_load $cap_load [all_outputs]
|
||||
|
||||
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
|
||||
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
|
||||
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
|
||||
|
||||
puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
|
||||
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {clock}]
|
||||
|
||||
puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
|
||||
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clock}]
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,74 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Thu Nov 25 13:15:53 2021
|
||||
###############################################################################
|
||||
current_design caravel_clocking
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name ext_clk -period 25.0000 [get_ports {ext_clk}]
|
||||
set_clock_transition 0.1500 [get_clocks {ext_clk}]
|
||||
set_clock_uncertainty 0.2500 ext_clk
|
||||
set_propagated_clock [get_clocks {ext_clk}]
|
||||
create_clock -name pll_clk -period 6.6667 [get_ports {pll_clk}]
|
||||
set_clock_transition 0.1500 [get_clocks {pll_clk}]
|
||||
set_clock_uncertainty 0.2500 pll_clk
|
||||
set_propagated_clock [get_clocks {pll_clk}]
|
||||
create_clock -name pll_clk90 -period 6.6667 [get_ports {pll_clk90}]
|
||||
set_clock_transition 0.1500 [get_clocks {pll_clk90}]
|
||||
set_clock_uncertainty 0.2500 pll_clk90
|
||||
set_propagated_clock [get_clocks {pll_clk90}]
|
||||
create_generated_clock -name pll_clk_divided -source [get_ports {pll_clk}] -divide_by 2 [get_pins {_351_/Y}]
|
||||
set_propagated_clock [get_clocks {pll_clk_divided}]
|
||||
create_generated_clock -name pll_clk90_divided -source [get_ports {pll_clk90}] -divide_by 2 [get_pins {_354_/Y}]
|
||||
set_propagated_clock [get_clocks {pll_clk90_divided}]
|
||||
create_generated_clock -name core_ext_clk_syncd -source [get_pins {_426_/Q}] -divide_by 1 [get_pins {_412_/X}]
|
||||
set_propagated_clock [get_clocks {core_ext_clk_syncd}]
|
||||
create_generated_clock -name core_clk_pll -source [get_pins {_351_/Y}] -divide_by 1 [get_pins {_393_/X}]
|
||||
set_propagated_clock [get_clocks {core_clk_pll}]
|
||||
create_generated_clock -name user_clk_pll -source [get_pins {_354_/Y}] -divide_by 1 [get_pins {_394_/X}]
|
||||
set_propagated_clock [get_clocks {user_clk_pll}]
|
||||
set_clock_groups -name group1 -logically_exclusive \
|
||||
-group [get_clocks {core_ext_clk_syncd}]
|
||||
set_clock_groups -name group2 -logically_exclusive \
|
||||
-group [get_clocks {core_clk_pll}]
|
||||
set_clock_groups -name group3 -logically_exclusive \
|
||||
-group [get_clocks {user_clk_pll}]
|
||||
set_clock_groups -name group4 -logically_exclusive \
|
||||
-group [get_clocks {ext_clk}]\
|
||||
-group [list [get_clocks {pll_clk}]\
|
||||
[get_clocks {pll_clk90}]\
|
||||
[get_clocks {pll_clk90_divided}]\
|
||||
[get_clocks {pll_clk_divided}]]
|
||||
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {ext_clk_sel}]
|
||||
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[0]}]
|
||||
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[1]}]
|
||||
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[2]}]
|
||||
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[0]}]
|
||||
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[1]}]
|
||||
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {resetb_sync}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {core_clk}]
|
||||
set_load -pin_load 0.0334 [get_ports {resetb_sync}]
|
||||
set_load -pin_load 0.0334 [get_ports {user_clk}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_clk}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_clk_sel}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_reset}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pll_clk}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pll_clk90}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel2[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel2[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel2[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 5.0000 [current_design]
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,95 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Thu Nov 18 17:35:10 2021
|
||||
###############################################################################
|
||||
current_design digital_pll
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name pll_control_clock -period 6.6667 [get_pins {ringosc.ibufp01/Y}]
|
||||
set_clock_transition 0.1500 [get_clocks {pll_control_clock}]
|
||||
set_clock_uncertainty 0.2500 pll_control_clock
|
||||
set_propagated_clock [get_clocks {pll_control_clock}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {dco}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {div[0]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {div[1]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {div[2]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {div[3]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {div[4]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {enable}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[0]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[10]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[11]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[12]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[13]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[14]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[15]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[16]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[17]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[18]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[19]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[1]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[20]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[21]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[22]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[23]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[24]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[25]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[2]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[3]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[4]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[5]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[6]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[7]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[8]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {ext_trim[9]}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {osc}]
|
||||
set_input_delay 2.0000 -add_delay [get_ports {resetb}]
|
||||
set_output_delay 2.0000 -add_delay [get_ports {clockp[0]}]
|
||||
set_output_delay 2.0000 -add_delay [get_ports {clockp[1]}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {clockp[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {clockp[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dco}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {enable}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {osc}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[25]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[24]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[23]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[22]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[21]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[20]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[19]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[18]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[17]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[16]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[15]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[14]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[13]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 6.0000 [current_design]
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,110 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Sat Nov 20 12:29:42 2021
|
||||
###############################################################################
|
||||
current_design gpio_control_block
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name serial_clock -period 50.0000 [get_ports {serial_clock}]
|
||||
set_clock_transition 0.1500 [get_clocks {serial_clock}]
|
||||
set_clock_uncertainty 0.2500 serial_clock
|
||||
set_propagated_clock [get_clocks {serial_clock}]
|
||||
create_clock -name serial_load -period 50.0000 [get_ports {serial_load}]
|
||||
set_clock_transition 0.1500 [get_clocks {serial_load}]
|
||||
set_clock_uncertainty 0.2500 serial_load
|
||||
set_propagated_clock [get_clocks {serial_load}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_out}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_in}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {resetn}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_in}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {one}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_en}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_pol}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_holdover}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_inenb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_outenb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_slow_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {resetn_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_clock_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {zero}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_in}]
|
||||
set_load -pin_load 0.0334 [get_ports {one}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_en}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_pol}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_holdover}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_inenb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_outenb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_slow_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {resetn_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_clock_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_data_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_load_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {user_gpio_in}]
|
||||
set_load -pin_load 0.0334 [get_ports {zero}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pad_gpio_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetn}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_clock}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_data_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_load}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 5.0000 [current_design]
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,45 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Fri Nov 5 21:10:28 2021
|
||||
###############################################################################
|
||||
current_design gpio_defaults_block
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name __VIRTUAL_CLK__ -period 10.0000
|
||||
set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[0]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[10]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[11]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[12]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[1]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[2]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[3]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[4]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[5]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[6]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[7]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[8]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_defaults[9]}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[12]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[11]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[10]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[9]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[8]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[7]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[6]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[5]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[4]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[3]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_defaults[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 5.0000 [current_design]
|
||||
|
|
@ -0,0 +1,273 @@
|
|||
*SPEF "ieee 1481-1999"
|
||||
*DESIGN "gpio_defaults_block"
|
||||
*DATE "11:11:11 Fri 11 11, 1111"
|
||||
*VENDOR "OpenRCX"
|
||||
*PROGRAM "Parallel Extraction"
|
||||
*VERSION "1.0"
|
||||
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
|
||||
*DIVIDER /
|
||||
*DELIMITER :
|
||||
*BUS_DELIMITER []
|
||||
*T_UNIT 1 NS
|
||||
*C_UNIT 1 PF
|
||||
*R_UNIT 1 OHM
|
||||
*L_UNIT 1 HENRY
|
||||
|
||||
*NAME_MAP
|
||||
*3 gpio_defaults_low\[0\]
|
||||
*4 gpio_defaults_high\[10\]
|
||||
*5 gpio_defaults_low\[11\]
|
||||
*6 gpio_defaults_low\[12\]
|
||||
*7 gpio_defaults_high\[1\]
|
||||
*8 gpio_defaults_low\[2\]
|
||||
*9 gpio_defaults_low\[3\]
|
||||
*10 gpio_defaults_low\[4\]
|
||||
*11 gpio_defaults_low\[5\]
|
||||
*12 gpio_defaults_low\[6\]
|
||||
*13 gpio_defaults_low\[7\]
|
||||
*14 gpio_defaults_low\[8\]
|
||||
*15 gpio_defaults_low\[9\]
|
||||
*16 gpio_defaults_high\[0\]
|
||||
*17 gpio_defaults_high\[11\]
|
||||
*18 gpio_defaults_high\[12\]
|
||||
*19 gpio_defaults_high\[2\]
|
||||
*20 gpio_defaults_high\[3\]
|
||||
*21 gpio_defaults_high\[4\]
|
||||
*22 gpio_defaults_high\[5\]
|
||||
*23 gpio_defaults_high\[6\]
|
||||
*24 gpio_defaults_high\[7\]
|
||||
*25 gpio_defaults_high\[8\]
|
||||
*26 gpio_defaults_high\[9\]
|
||||
*27 gpio_defaults_low\[10\]
|
||||
*28 gpio_defaults_low\[1\]
|
||||
*29 FILLER_0_29
|
||||
*30 FILLER_0_3
|
||||
*31 FILLER_0_33
|
||||
*32 FILLER_0_38
|
||||
*33 FILLER_0_43
|
||||
*34 FILLER_0_48
|
||||
*35 FILLER_0_55
|
||||
*36 FILLER_0_60
|
||||
*37 FILLER_0_9
|
||||
*38 FILLER_1_15
|
||||
*39 FILLER_1_27
|
||||
*40 FILLER_1_3
|
||||
*41 FILLER_1_39
|
||||
*42 FILLER_1_51
|
||||
*43 FILLER_1_55
|
||||
*44 FILLER_1_57
|
||||
*45 FILLER_1_61
|
||||
*46 FILLER_2_15
|
||||
*47 FILLER_2_27
|
||||
*48 FILLER_2_29
|
||||
*49 FILLER_2_3
|
||||
*50 FILLER_2_41
|
||||
*51 FILLER_2_53
|
||||
*52 FILLER_2_57
|
||||
*53 FILLER_2_61
|
||||
*54 PHY_0
|
||||
*55 PHY_1
|
||||
*56 PHY_2
|
||||
*57 PHY_3
|
||||
*58 PHY_4
|
||||
*59 PHY_5
|
||||
*60 TAP_10
|
||||
*61 TAP_6
|
||||
*62 TAP_7
|
||||
*63 TAP_8
|
||||
*64 TAP_9
|
||||
*65 gpio_default_value\[0\]
|
||||
*66 gpio_default_value\[10\]
|
||||
*67 gpio_default_value\[11\]
|
||||
*68 gpio_default_value\[12\]
|
||||
*69 gpio_default_value\[1\]
|
||||
*70 gpio_default_value\[2\]
|
||||
*71 gpio_default_value\[3\]
|
||||
*72 gpio_default_value\[4\]
|
||||
*73 gpio_default_value\[5\]
|
||||
*74 gpio_default_value\[6\]
|
||||
*75 gpio_default_value\[7\]
|
||||
*76 gpio_default_value\[8\]
|
||||
*77 gpio_default_value\[9\]
|
||||
|
||||
*PORTS
|
||||
gpio_defaults[0] O
|
||||
gpio_defaults[10] O
|
||||
gpio_defaults[11] O
|
||||
gpio_defaults[12] O
|
||||
gpio_defaults[1] O
|
||||
gpio_defaults[2] O
|
||||
gpio_defaults[3] O
|
||||
gpio_defaults[4] O
|
||||
gpio_defaults[5] O
|
||||
gpio_defaults[6] O
|
||||
gpio_defaults[7] O
|
||||
gpio_defaults[8] O
|
||||
gpio_defaults[9] O
|
||||
|
||||
*D_NET *3 0.000662868
|
||||
*CONN
|
||||
*P gpio_defaults[0] O
|
||||
*I *65:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[0] 0.000295589
|
||||
2 *65:LO 0.000295589
|
||||
3 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
|
||||
*RES
|
||||
1 *65:LO gpio_defaults[0] 21.1394
|
||||
*END
|
||||
|
||||
*D_NET *4 0.000169932
|
||||
*CONN
|
||||
*P gpio_defaults[10] O
|
||||
*I *66:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[10] 8.49658e-05
|
||||
2 *66:HI 8.49658e-05
|
||||
3 gpio_defaults[10] gpio_defaults[11] 0
|
||||
4 gpio_defaults[10] gpio_defaults[9] 0
|
||||
*RES
|
||||
1 *66:HI gpio_defaults[10] 15.7033
|
||||
*END
|
||||
|
||||
*D_NET *5 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[11] O
|
||||
*I *67:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[11] 0.000115448
|
||||
2 *67:LO 0.000115448
|
||||
3 gpio_defaults[11] gpio_defaults[12] 0
|
||||
4 gpio_defaults[10] gpio_defaults[11] 0
|
||||
*RES
|
||||
1 *67:LO gpio_defaults[11] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *6 0.000822209
|
||||
*CONN
|
||||
*P gpio_defaults[12] O
|
||||
*I *68:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[12] 0.000411104
|
||||
2 *68:LO 0.000411104
|
||||
3 gpio_defaults[11] gpio_defaults[12] 0
|
||||
*RES
|
||||
1 *68:LO gpio_defaults[12] 23.2185
|
||||
*END
|
||||
|
||||
*D_NET *7 0.00071336
|
||||
*CONN
|
||||
*P gpio_defaults[1] O
|
||||
*I *69:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[1] 0.000307544
|
||||
2 *69:HI 0.000307544
|
||||
3 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
|
||||
4 gpio_defaults[0] gpio_defaults[1] 7.16893e-05
|
||||
*RES
|
||||
1 *69:HI gpio_defaults[1] 19.1997
|
||||
*END
|
||||
|
||||
*D_NET *8 0.000464143
|
||||
*CONN
|
||||
*P gpio_defaults[2] O
|
||||
*I *70:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[2] 0.00021878
|
||||
2 *70:LO 0.00021878
|
||||
3 gpio_defaults[2] gpio_defaults[3] 0
|
||||
4 gpio_defaults[1] gpio_defaults[2] 2.65831e-05
|
||||
*RES
|
||||
1 *70:LO gpio_defaults[2] 18.921
|
||||
*END
|
||||
|
||||
*D_NET *9 0.000363376
|
||||
*CONN
|
||||
*P gpio_defaults[3] O
|
||||
*I *71:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[3] 0.000181688
|
||||
2 *71:LO 0.000181688
|
||||
3 gpio_defaults[3] gpio_defaults[4] 0
|
||||
4 gpio_defaults[2] gpio_defaults[3] 0
|
||||
*RES
|
||||
1 *71:LO gpio_defaults[3] 17.8118
|
||||
*END
|
||||
|
||||
*D_NET *10 0.000236028
|
||||
*CONN
|
||||
*P gpio_defaults[4] O
|
||||
*I *72:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[4] 0.000118014
|
||||
2 *72:LO 0.000118014
|
||||
3 gpio_defaults[4] gpio_defaults[5] 0
|
||||
4 gpio_defaults[3] gpio_defaults[4] 0
|
||||
*RES
|
||||
1 *72:LO gpio_defaults[4] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *11 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[5] O
|
||||
*I *73:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[5] 0.000115448
|
||||
2 *73:LO 0.000115448
|
||||
3 gpio_defaults[5] gpio_defaults[6] 0
|
||||
4 gpio_defaults[4] gpio_defaults[5] 0
|
||||
*RES
|
||||
1 *73:LO gpio_defaults[5] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *12 0.000230895
|
||||
*CONN
|
||||
*P gpio_defaults[6] O
|
||||
*I *74:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[6] 0.000115448
|
||||
2 *74:LO 0.000115448
|
||||
3 gpio_defaults[6] gpio_defaults[7] 0
|
||||
4 gpio_defaults[5] gpio_defaults[6] 0
|
||||
*RES
|
||||
1 *74:LO gpio_defaults[6] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *13 0.00022764
|
||||
*CONN
|
||||
*P gpio_defaults[7] O
|
||||
*I *75:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[7] 0.00011382
|
||||
2 *75:LO 0.00011382
|
||||
3 gpio_defaults[7] gpio_defaults[8] 0
|
||||
4 gpio_defaults[6] gpio_defaults[7] 0
|
||||
*RES
|
||||
1 *75:LO gpio_defaults[7] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *14 0.000224385
|
||||
*CONN
|
||||
*P gpio_defaults[8] O
|
||||
*I *76:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[8] 0.000112192
|
||||
2 *76:LO 0.000112192
|
||||
3 gpio_defaults[8] gpio_defaults[9] 0
|
||||
4 gpio_defaults[7] gpio_defaults[8] 0
|
||||
*RES
|
||||
1 *76:LO gpio_defaults[8] 16.5338
|
||||
*END
|
||||
|
||||
*D_NET *15 0.00022764
|
||||
*CONN
|
||||
*P gpio_defaults[9] O
|
||||
*I *77:LO O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_defaults[9] 0.00011382
|
||||
2 *77:LO 0.00011382
|
||||
3 gpio_defaults[10] gpio_defaults[9] 0
|
||||
4 gpio_defaults[8] gpio_defaults[9] 0
|
||||
*RES
|
||||
1 *77:LO gpio_defaults[9] 16.5338
|
||||
*END
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Fri Nov 5 09:51:10 2021
|
||||
###############################################################################
|
||||
current_design gpio_logic_high
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name __VIRTUAL_CLK__ -period 10.0000
|
||||
set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {gpio_logic1}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {gpio_logic1}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 5.0000 [current_design]
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
*SPEF "ieee 1481-1999"
|
||||
*DESIGN "gpio_logic_high"
|
||||
*DATE "11:11:11 Fri 11 11, 1111"
|
||||
*VENDOR "OpenRCX"
|
||||
*PROGRAM "Parallel Extraction"
|
||||
*VERSION "1.0"
|
||||
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
|
||||
*DIVIDER /
|
||||
*DELIMITER :
|
||||
*BUS_DELIMITER []
|
||||
*T_UNIT 1 NS
|
||||
*C_UNIT 1 PF
|
||||
*R_UNIT 1 OHM
|
||||
*L_UNIT 1 HENRY
|
||||
|
||||
*NAME_MAP
|
||||
*1 gpio_logic1
|
||||
*2 FILLER_0_3
|
||||
*3 FILLER_0_7
|
||||
*4 FILLER_0_9
|
||||
*5 FILLER_1_11
|
||||
*6 FILLER_1_3
|
||||
*7 FILLER_2_3
|
||||
*8 FILLER_2_7
|
||||
*9 FILLER_2_9
|
||||
*10 FILLER_3_3
|
||||
*11 FILLER_4_3
|
||||
*12 FILLER_4_7
|
||||
*13 FILLER_4_9
|
||||
*14 PHY_0
|
||||
*15 PHY_1
|
||||
*16 PHY_2
|
||||
*17 PHY_3
|
||||
*18 PHY_4
|
||||
*19 PHY_5
|
||||
*20 PHY_6
|
||||
*21 PHY_7
|
||||
*22 PHY_8
|
||||
*23 PHY_9
|
||||
*24 TAP_10
|
||||
*25 TAP_11
|
||||
*26 TAP_12
|
||||
*27 gpio_logic_high
|
||||
|
||||
*PORTS
|
||||
gpio_logic1 O
|
||||
|
||||
*D_NET *1 0.000513616
|
||||
*CONN
|
||||
*P gpio_logic1 O
|
||||
*I *27:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 gpio_logic1 0.000256808
|
||||
2 *27:HI 0.000256808
|
||||
*RES
|
||||
1 *27:HI gpio_logic1 21.9631
|
||||
*END
|
||||
|
|
@ -0,0 +1,823 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Wed Nov 24 20:39:01 2021
|
||||
###############################################################################
|
||||
current_design housekeeping
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name wb_clk_i -period 25.0000 [get_ports {wb_clk_i}]
|
||||
set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
|
||||
set_clock_uncertainty 0.2500 wb_clk_i
|
||||
set_propagated_clock [get_clocks {wb_clk_i}]
|
||||
create_clock -name mgmt_gpio_in -period 100.0000 [get_ports {mgmt_gpio_in[4]}]
|
||||
set_clock_transition 0.1500 [get_clocks {mgmt_gpio_in}]
|
||||
set_clock_uncertainty 0.2500 mgmt_gpio_in
|
||||
set_propagated_clock [get_clocks {mgmt_gpio_in}]
|
||||
create_generated_clock -name wbbd_sck -source [get_ports {wb_clk_i}] -divide_by 1 [get_pins {_9640_/Q}]
|
||||
set_propagated_clock [get_clocks {wbbd_sck}]
|
||||
create_generated_clock -name csclk_slow -source [get_ports {mgmt_gpio_in[4]}] -divide_by 1 [get_pins {_8847_/X}]
|
||||
set_propagated_clock [get_clocks {csclk_slow}]
|
||||
set_clock_groups -name group1 -logically_exclusive \
|
||||
-group [get_clocks {mgmt_gpio_in}]\
|
||||
-group [get_clocks {wb_clk_i}]
|
||||
set_clock_groups -name group2 -logically_exclusive \
|
||||
-group [get_clocks {csclk_slow}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_mode}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_oeb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_out}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[0]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[10]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[11]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[12]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[13]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[14]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[15]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[16]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[17]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[18]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[19]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[1]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[20]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[21]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[22]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[23]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[24]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[25]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[26]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[27]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[28]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[29]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[2]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[30]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[31]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[3]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[4]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[5]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[6]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[7]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[8]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[9]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[0]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[10]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[11]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[12]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[13]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[14]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[15]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[16]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[17]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[18]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[19]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[1]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[20]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[21]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[22]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[23]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[24]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[25]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[26]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[27]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[28]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[29]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[2]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[30]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[31]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[32]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[33]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[34]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[35]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[36]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[37]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[3]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[5]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[6]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[7]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[8]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[9]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_di}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_di}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {porb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {qspi_enabled}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_tx}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_csb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_enabled}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sck}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdo}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdoenb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_clk}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_csb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_do}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_oeb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_do}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_oeb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_do}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_oeb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_do}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_oeb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[0]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[10]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[11]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[12]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[13]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[14]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[15]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[16]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[17]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[18]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[19]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[1]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[20]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[21]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[22]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[23]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[24]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[25]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[26]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[27]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[28]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[29]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[2]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[30]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[31]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[3]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[4]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[5]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[6]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[7]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[8]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_data[9]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {trap}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {uart_enabled}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_clock}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vcc_pwrgood}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vdd_pwrgood}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vcc_pwrgood}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vdd_pwrgood}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[0]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[10]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[11]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[12]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[13]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[14]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[15]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[16]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[17]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[18]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[19]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[1]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[20]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[21]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[22]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[23]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[24]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[25]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[26]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[27]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[28]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[29]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[2]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[30]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[31]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[3]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[4]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[5]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[6]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[7]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[8]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[9]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[0]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[10]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[11]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[12]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[13]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[14]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[15]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[16]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[17]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[18]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[19]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[1]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[20]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[21]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[22]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[23]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[24]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[25]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[26]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[27]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[28]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[29]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[2]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[30]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[31]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[3]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[4]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[5]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[6]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[7]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[8]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[9]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rstn_i}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[0]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[1]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[2]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[3]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_in}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[10]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[11]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[12]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[13]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[14]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[15]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[16]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[17]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[18]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[19]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[20]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[21]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[22]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[23]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[24]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[25]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[26]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[27]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[28]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[29]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[30]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[31]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[32]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[33]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[34]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[35]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[36]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[37]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[4]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[5]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[6]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[7]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[8]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[9]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[10]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[11]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[12]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[13]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[14]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[15]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[16]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[17]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[18]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[19]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[20]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[21]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[22]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[23]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[24]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[25]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[26]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[27]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[28]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[29]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[30]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[31]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[32]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[33]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[34]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[35]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[36]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[37]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[4]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[5]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[6]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[7]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[8]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[9]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk_oeb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb_oeb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_do}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_ieb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_oeb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_do}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_ieb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_oeb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_bypass}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_dco_ena}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[4]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_ena}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[10]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[11]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[12]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[13]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[14]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[15]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[16]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[17]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[18]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[19]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[20]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[21]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[22]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[23]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[24]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[25]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[4]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[5]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[6]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[7]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[8]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[9]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {reset}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_rx}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_clock}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_1}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_2}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_load}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_resetn}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdi}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_di}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_di}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_di}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_di}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_addr[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_addr[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_addr[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_addr[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_addr[4]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_addr[5]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_addr[6]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_addr[7]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_clk}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {sram_ro_csb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[10]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[11]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[12]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[13]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[14]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[15]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[16]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[17]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[18]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[19]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[20]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[21]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[22]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[23]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[24]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[25]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[26]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[27]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[28]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[29]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[30]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[31]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[4]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[5]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[6]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[7]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[8]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[9]}]
|
||||
set_false_path\
|
||||
-from [list [get_ports {porb}]\
|
||||
[get_ports {wb_rstn_i}]]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {debug_in}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_flash_clk}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_flash_clk_oeb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_flash_csb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_flash_csb_oeb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_flash_io0_do}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_flash_io0_ieb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_flash_io0_oeb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_flash_io1_do}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_flash_io1_ieb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_flash_io1_oeb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_bypass}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_dco_ena}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_ena}]
|
||||
set_load -pin_load 0.0334 [get_ports {reset}]
|
||||
set_load -pin_load 0.0334 [get_ports {ser_rx}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_clock}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_data_1}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_data_2}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_load}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_resetn}]
|
||||
set_load -pin_load 0.0334 [get_ports {spi_sdi}]
|
||||
set_load -pin_load 0.0334 [get_ports {spimemio_flash_io0_di}]
|
||||
set_load -pin_load 0.0334 [get_ports {spimemio_flash_io1_di}]
|
||||
set_load -pin_load 0.0334 [get_ports {spimemio_flash_io2_di}]
|
||||
set_load -pin_load 0.0334 [get_ports {spimemio_flash_io3_di}]
|
||||
set_load -pin_load 0.0334 [get_ports {sram_ro_clk}]
|
||||
set_load -pin_load 0.0334 [get_ports {sram_ro_csb}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_ack_o}]
|
||||
set_load -pin_load 0.0334 [get_ports {irq[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {irq[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {irq[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[37]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[36]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[35]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[34]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[33]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[32]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[31]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[30]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[29]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[28]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[27]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[26]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[25]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[24]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[23]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[22]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[21]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[20]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[19]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[18]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[17]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[16]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[15]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[14]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[13]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[12]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[11]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[10]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[9]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[8]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[7]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[6]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[5]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[4]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[3]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_oeb[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[37]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[36]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[35]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[34]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[33]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[32]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[31]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[30]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[29]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[28]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[27]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[26]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[25]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[24]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[23]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[22]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[21]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[20]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[19]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[18]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[17]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[16]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[15]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[14]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[13]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[12]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[11]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[10]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[9]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[8]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[7]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[6]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[5]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[4]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[3]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_out[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll90_sel[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll90_sel[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll90_sel[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_div[4]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_div[3]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_div[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_div[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_div[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_sel[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_sel[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_sel[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[25]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[24]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[23]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[22]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[21]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[20]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[19]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[18]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[17]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[16]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[15]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[14]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[13]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[12]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[11]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[10]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[9]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[8]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[7]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[6]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[5]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[4]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[3]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pll_trim[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pwr_ctrl_out[3]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pwr_ctrl_out[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pwr_ctrl_out[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pwr_ctrl_out[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {sram_ro_addr[7]}]
|
||||
set_load -pin_load 0.0334 [get_ports {sram_ro_addr[6]}]
|
||||
set_load -pin_load 0.0334 [get_ports {sram_ro_addr[5]}]
|
||||
set_load -pin_load 0.0334 [get_ports {sram_ro_addr[4]}]
|
||||
set_load -pin_load 0.0334 [get_ports {sram_ro_addr[3]}]
|
||||
set_load -pin_load 0.0334 [get_ports {sram_ro_addr[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {sram_ro_addr[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {sram_ro_addr[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[31]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[30]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[29]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[28]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[27]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[26]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[25]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[24]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[23]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[22]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[21]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[20]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[19]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[18]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[17]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[16]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[15]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[14]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[13]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[12]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[11]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[10]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[9]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[8]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[7]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[6]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[5]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[4]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[3]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {wb_dat_o[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_mode}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {debug_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pad_flash_io0_di}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pad_flash_io1_di}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {porb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {qspi_enabled}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ser_tx}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_csb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_enabled}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sck}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdo}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdoenb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spimemio_flash_clk}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spimemio_flash_csb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spimemio_flash_io0_do}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spimemio_flash_io0_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spimemio_flash_io1_do}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spimemio_flash_io1_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spimemio_flash_io2_do}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spimemio_flash_io2_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spimemio_flash_io3_do}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spimemio_flash_io3_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {trap}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_enabled}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usr1_vcc_pwrgood}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usr1_vdd_pwrgood}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usr2_vcc_pwrgood}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usr2_vdd_pwrgood}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rstn_i}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_stb_i}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[31]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[30]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[29]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[28]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[27]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[26]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[25]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[24]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[23]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[22]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[21]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[20]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[19]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[18]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[17]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[16]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[15]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[14]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[13]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mask_rev_in[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[37]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[36]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[35]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[34]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[33]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[32]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[31]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[30]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[29]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[28]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[27]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[26]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[25]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[24]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[23]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[22]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[21]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[20]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[19]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[18]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[17]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[16]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[15]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[14]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[13]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_in[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[31]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[30]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[29]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[28]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[27]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[26]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[25]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[24]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[23]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[22]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[21]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[20]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[19]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[18]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[17]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[16]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[15]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[14]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[13]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_ro_data[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[31]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[30]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[29]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[28]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[27]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[26]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[25]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[24]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[23]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[22]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[21]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[20]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[19]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[18]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[17]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[16]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[15]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[14]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[13]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[31]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[30]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[29]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[28]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[27]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[26]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[25]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[24]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[23]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[22]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[21]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[20]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[19]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[18]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[17]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[16]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[15]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[14]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[13]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 20.0000 [current_design]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,21 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Mon Nov 15 10:50:21 2021
|
||||
###############################################################################
|
||||
current_design mprj2_logic_high
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name __VIRTUAL_CLK__ -period 10.0000
|
||||
set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {HI}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 5.0000 [current_design]
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
*SPEF "ieee 1481-1999"
|
||||
*DESIGN "mprj2_logic_high"
|
||||
*DATE "11:11:11 Fri 11 11, 1111"
|
||||
*VENDOR "OpenRCX"
|
||||
*PROGRAM "Parallel Extraction"
|
||||
*VERSION "1.0"
|
||||
*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
|
||||
*DIVIDER /
|
||||
*DELIMITER :
|
||||
*BUS_DELIMITER []
|
||||
*T_UNIT 1 NS
|
||||
*C_UNIT 1 PF
|
||||
*R_UNIT 1 OHM
|
||||
*L_UNIT 1 HENRY
|
||||
|
||||
*NAME_MAP
|
||||
*1 HI
|
||||
*2 FILLER_0_109
|
||||
*3 FILLER_0_113
|
||||
*4 FILLER_0_125
|
||||
*5 FILLER_0_137
|
||||
*6 FILLER_0_141
|
||||
*7 FILLER_0_15
|
||||
*8 FILLER_0_153
|
||||
*9 FILLER_0_165
|
||||
*10 FILLER_0_169
|
||||
*11 FILLER_0_181
|
||||
*12 FILLER_0_193
|
||||
*13 FILLER_0_197
|
||||
*14 FILLER_0_209
|
||||
*15 FILLER_0_213
|
||||
*16 FILLER_0_27
|
||||
*17 FILLER_0_29
|
||||
*18 FILLER_0_3
|
||||
*19 FILLER_0_41
|
||||
*20 FILLER_0_53
|
||||
*21 FILLER_0_57
|
||||
*22 FILLER_0_69
|
||||
*23 FILLER_0_81
|
||||
*24 FILLER_0_85
|
||||
*25 FILLER_0_97
|
||||
*26 FILLER_1_107
|
||||
*27 FILLER_1_111
|
||||
*28 FILLER_1_113
|
||||
*29 FILLER_1_125
|
||||
*30 FILLER_1_137
|
||||
*31 FILLER_1_141
|
||||
*32 FILLER_1_15
|
||||
*33 FILLER_1_153
|
||||
*34 FILLER_1_165
|
||||
*35 FILLER_1_169
|
||||
*36 FILLER_1_181
|
||||
*37 FILLER_1_193
|
||||
*38 FILLER_1_197
|
||||
*39 FILLER_1_209
|
||||
*40 FILLER_1_213
|
||||
*41 FILLER_1_27
|
||||
*42 FILLER_1_29
|
||||
*43 FILLER_1_3
|
||||
*44 FILLER_1_41
|
||||
*45 FILLER_1_53
|
||||
*46 FILLER_1_57
|
||||
*47 FILLER_1_69
|
||||
*48 FILLER_1_81
|
||||
*49 FILLER_1_85
|
||||
*50 FILLER_1_91
|
||||
*51 FILLER_1_95
|
||||
*52 PHY_0
|
||||
*53 PHY_1
|
||||
*54 PHY_2
|
||||
*55 PHY_3
|
||||
*56 TAP_10
|
||||
*57 TAP_11
|
||||
*58 TAP_12
|
||||
*59 TAP_13
|
||||
*60 TAP_14
|
||||
*61 TAP_15
|
||||
*62 TAP_16
|
||||
*63 TAP_17
|
||||
*64 TAP_4
|
||||
*65 TAP_5
|
||||
*66 TAP_6
|
||||
*67 TAP_7
|
||||
*68 TAP_8
|
||||
*69 TAP_9
|
||||
*70 inst
|
||||
|
||||
*PORTS
|
||||
HI O
|
||||
|
||||
*D_NET *1 0.00667596
|
||||
*CONN
|
||||
*P HI O
|
||||
*I *70:HI O *D sky130_fd_sc_hd__conb_1
|
||||
*CAP
|
||||
1 HI 0.00333798
|
||||
2 *70:HI 0.00333798
|
||||
*RES
|
||||
1 *70:HI HI 24.0614
|
||||
*END
|
||||
|
|
@ -0,0 +1,945 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Wed Nov 17 17:45:16 2021
|
||||
###############################################################################
|
||||
current_design mprj_logic_high
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name __VIRTUAL_CLK__ -period 10.0000
|
||||
set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[0]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[100]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[101]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[102]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[103]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[104]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[105]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[106]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[107]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[108]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[109]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[10]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[110]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[111]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[112]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[113]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[114]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[115]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[116]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[117]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[118]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[119]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[11]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[120]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[121]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[122]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[123]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[124]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[125]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[126]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[127]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[128]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[129]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[12]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[130]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[131]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[132]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[133]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[134]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[135]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[136]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[137]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[138]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[139]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[13]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[140]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[141]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[142]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[143]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[144]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[145]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[146]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[147]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[148]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[149]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[14]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[150]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[151]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[152]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[153]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[154]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[155]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[156]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[157]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[158]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[159]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[15]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[160]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[161]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[162]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[163]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[164]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[165]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[166]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[167]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[168]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[169]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[16]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[170]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[171]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[172]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[173]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[174]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[175]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[176]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[177]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[178]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[179]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[17]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[180]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[181]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[182]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[183]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[184]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[185]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[186]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[187]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[188]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[189]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[18]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[190]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[191]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[192]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[193]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[194]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[195]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[196]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[197]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[198]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[199]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[19]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[1]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[200]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[201]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[202]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[203]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[204]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[205]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[206]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[207]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[208]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[209]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[20]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[210]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[211]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[212]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[213]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[214]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[215]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[216]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[217]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[218]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[219]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[21]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[220]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[221]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[222]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[223]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[224]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[225]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[226]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[227]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[228]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[229]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[22]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[230]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[231]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[232]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[233]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[234]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[235]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[236]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[237]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[238]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[239]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[23]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[240]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[241]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[242]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[243]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[244]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[245]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[246]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[247]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[248]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[249]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[24]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[250]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[251]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[252]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[253]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[254]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[255]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[256]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[257]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[258]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[259]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[25]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[260]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[261]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[262]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[263]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[264]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[265]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[266]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[267]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[268]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[269]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[26]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[270]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[271]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[272]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[273]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[274]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[275]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[276]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[277]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[278]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[279]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[27]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[280]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[281]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[282]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[283]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[284]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[285]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[286]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[287]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[288]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[289]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[28]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[290]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[291]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[292]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[293]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[294]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[295]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[296]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[297]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[298]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[299]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[29]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[2]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[300]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[301]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[302]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[303]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[304]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[305]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[306]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[307]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[308]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[309]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[30]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[310]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[311]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[312]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[313]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[314]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[315]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[316]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[317]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[318]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[319]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[31]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[320]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[321]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[322]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[323]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[324]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[325]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[326]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[327]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[328]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[329]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[32]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[330]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[331]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[332]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[333]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[334]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[335]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[336]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[337]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[338]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[339]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[33]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[340]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[341]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[342]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[343]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[344]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[345]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[346]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[347]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[348]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[349]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[34]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[350]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[351]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[352]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[353]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[354]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[355]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[356]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[357]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[358]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[359]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[35]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[360]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[361]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[362]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[363]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[364]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[365]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[366]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[367]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[368]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[369]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[36]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[370]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[371]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[372]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[373]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[374]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[375]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[376]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[377]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[378]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[379]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[37]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[380]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[381]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[382]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[383]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[384]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[385]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[386]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[387]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[388]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[389]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[38]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[390]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[391]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[392]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[393]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[394]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[395]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[396]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[397]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[398]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[399]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[39]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[3]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[400]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[401]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[402]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[403]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[404]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[405]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[406]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[407]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[408]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[409]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[40]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[410]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[411]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[412]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[413]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[414]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[415]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[416]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[417]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[418]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[419]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[41]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[420]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[421]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[422]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[423]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[424]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[425]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[426]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[427]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[428]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[429]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[42]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[430]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[431]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[432]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[433]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[434]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[435]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[436]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[437]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[438]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[439]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[43]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[440]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[441]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[442]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[443]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[444]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[445]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[446]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[447]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[448]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[449]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[44]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[450]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[451]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[452]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[453]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[454]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[455]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[456]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[457]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[458]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[459]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[45]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[460]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[461]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[462]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[46]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[47]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[48]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[49]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[4]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[50]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[51]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[52]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[53]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[54]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[55]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[56]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[57]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[58]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[59]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[5]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[60]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[61]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[62]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[63]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[64]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[65]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[66]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[67]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[68]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[69]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[6]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[70]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[71]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[72]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[73]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[74]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[75]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[76]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[77]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[78]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[79]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[7]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[80]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[81]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[82]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[83]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[84]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[85]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[86]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[87]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[88]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[89]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[8]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[90]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[91]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[92]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[93]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[94]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[95]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[96]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[97]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[98]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[99]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {HI[9]}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {HI[462]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[461]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[460]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[459]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[458]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[457]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[456]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[455]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[454]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[453]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[452]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[451]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[450]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[449]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[448]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[447]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[446]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[445]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[444]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[443]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[442]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[441]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[440]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[439]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[438]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[437]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[436]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[435]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[434]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[433]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[432]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[431]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[430]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[429]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[428]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[427]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[426]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[425]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[424]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[423]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[422]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[421]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[420]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[419]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[418]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[417]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[416]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[415]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[414]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[413]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[412]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[411]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[410]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[409]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[408]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[407]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[406]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[405]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[404]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[403]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[402]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[401]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[400]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[399]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[398]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[397]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[396]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[395]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[394]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[393]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[392]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[391]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[390]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[389]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[388]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[387]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[386]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[385]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[384]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[383]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[382]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[381]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[380]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[379]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[378]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[377]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[376]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[375]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[374]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[373]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[372]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[371]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[370]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[369]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[368]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[367]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[366]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[365]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[364]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[363]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[362]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[361]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[360]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[359]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[358]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[357]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[356]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[355]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[354]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[353]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[352]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[351]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[350]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[349]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[348]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[347]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[346]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[345]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[344]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[343]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[342]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[341]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[340]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[339]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[338]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[337]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[336]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[335]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[334]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[333]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[332]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[331]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[330]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[329]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[328]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[327]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[326]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[325]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[324]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[323]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[322]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[321]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[320]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[319]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[318]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[317]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[316]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[315]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[314]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[313]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[312]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[311]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[310]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[309]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[308]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[307]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[306]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[305]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[304]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[303]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[302]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[301]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[300]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[299]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[298]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[297]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[296]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[295]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[294]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[293]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[292]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[291]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[290]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[289]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[288]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[287]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[286]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[285]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[284]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[283]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[282]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[281]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[280]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[279]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[278]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[277]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[276]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[275]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[274]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[273]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[272]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[271]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[270]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[269]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[268]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[267]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[266]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[265]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[264]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[263]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[262]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[261]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[260]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[259]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[258]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[257]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[256]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[255]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[254]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[253]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[252]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[251]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[250]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[249]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[248]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[247]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[246]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[245]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[244]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[243]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[242]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[241]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[240]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[239]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[238]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[237]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[236]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[235]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[234]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[233]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[232]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[231]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[230]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[229]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[228]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[227]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[226]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[225]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[224]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[223]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[222]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[221]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[220]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[219]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[218]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[217]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[216]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[215]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[214]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[213]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[212]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[211]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[210]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[209]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[208]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[207]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[206]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[205]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[204]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[203]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[202]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[201]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[200]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[199]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[198]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[197]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[196]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[195]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[194]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[193]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[192]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[191]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[190]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[189]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[188]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[187]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[186]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[185]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[184]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[183]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[182]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[181]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[180]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[179]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[178]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[177]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[176]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[175]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[174]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[173]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[172]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[171]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[170]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[169]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[168]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[167]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[166]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[165]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[164]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[163]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[162]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[161]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[160]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[159]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[158]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[157]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[156]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[155]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[154]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[153]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[152]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[151]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[150]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[149]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[148]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[147]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[146]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[145]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[144]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[143]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[142]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[141]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[140]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[139]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[138]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[137]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[136]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[135]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[134]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[133]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[132]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[131]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[130]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[129]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[128]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[127]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[126]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[125]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[124]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[123]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[122]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[121]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[120]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[119]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[118]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[117]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[116]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[115]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[114]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[113]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[112]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[111]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[110]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[109]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[108]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[107]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[106]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[105]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[104]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[103]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[102]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[101]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[100]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[99]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[98]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[97]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[96]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[95]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[94]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[93]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[92]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[91]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[90]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[89]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[88]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[87]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[86]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[85]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[84]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[83]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[82]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[81]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[80]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[79]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[78]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[77]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[76]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[75]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[74]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[73]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[72]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[71]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[70]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[69]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[68]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[67]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[66]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[65]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[64]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[63]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[62]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[61]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[60]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[59]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[58]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[57]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[56]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[55]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[54]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[53]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[52]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[51]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[50]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[49]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[48]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[47]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[46]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[45]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[44]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[43]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[42]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[41]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[40]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[39]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[38]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[37]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[36]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[35]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[34]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[33]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[32]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[31]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[30]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[29]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[28]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[27]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[26]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[25]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[24]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[23]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[22]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[21]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[20]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[19]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[18]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[17]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[16]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[15]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[14]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[13]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[12]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[11]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[10]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[9]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[8]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[7]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[6]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[5]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[4]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[3]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {HI[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 5.0000 [current_design]
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,103 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Wed Nov 24 18:33:22 2021
|
||||
###############################################################################
|
||||
current_design spare_logic_block
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
create_clock -name __VIRTUAL_CLK__ -period 10.0000
|
||||
set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xfq[0]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xfq[1]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xfqn[0]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xfqn[1]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xi[0]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xi[1]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xi[2]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xi[3]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xib}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xmx[0]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xmx[1]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xna[0]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xna[1]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xno[0]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xno[1]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[0]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[10]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[11]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[12]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[13]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[14]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[15]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[16]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[17]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[18]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[19]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[1]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[20]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[21]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[22]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[23]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[24]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[25]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[26]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[2]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[3]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[4]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[5]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[6]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[7]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[8]}]
|
||||
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {spare_xz[9]}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xib}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xfq[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xfq[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xfqn[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xfqn[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xi[3]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xi[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xi[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xi[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xmx[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xmx[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xna[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xna[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xno[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xno[0]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[26]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[25]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[24]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[23]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[22]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[21]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[20]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[19]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[18]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[17]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[16]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[15]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[14]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[13]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[12]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[11]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[10]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[9]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[8]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[7]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[6]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[5]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[4]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[3]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {spare_xz[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 5.0000 [current_design]
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue