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caravel
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caravel/verilog/gl/caravel_clocking.v

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[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
module caravel_clocking (VGND,
VPWR,
core_clk,
ext_clk,
ext_clk_sel,
ext_reset,
pll_clk,
pll_clk90,
resetb,
resetb_sync,
user_clk,
sel,
sel2);
input VGND;
input VPWR;
output core_clk;
input ext_clk;
input ext_clk_sel;
input ext_reset;
input pll_clk;
input pll_clk90;
input resetb;
output resetb_sync;
output user_clk;
input [2:0] sel;
input [2:0] sel2;
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
wire clknet_0_ext_clk;
wire clknet_0_pll_clk;
wire clknet_0_pll_clk90;
wire clknet_1_0_0_ext_clk;
wire clknet_1_0_0_pll_clk;
wire clknet_1_0_0_pll_clk90;
wire clknet_1_1_0_ext_clk;
wire clknet_1_1_0_pll_clk;
wire clknet_1_1_0_pll_clk90;
wire \divider.even_0.N[0] ;
wire \divider.even_0.N[1] ;
wire \divider.even_0.N[2] ;
wire \divider.even_0.counter[0] ;
wire \divider.even_0.counter[1] ;
wire \divider.even_0.counter[2] ;
wire \divider.even_0.out_counter ;
wire \divider.odd_0.counter2[0] ;
wire \divider.odd_0.counter2[1] ;
wire \divider.odd_0.counter2[2] ;
wire \divider.odd_0.counter[0] ;
wire \divider.odd_0.counter[1] ;
wire \divider.odd_0.counter[2] ;
wire \divider.odd_0.initial_begin[0] ;
wire \divider.odd_0.initial_begin[1] ;
wire \divider.odd_0.initial_begin[2] ;
wire \divider.odd_0.old_N[0] ;
wire \divider.odd_0.old_N[1] ;
wire \divider.odd_0.old_N[2] ;
wire \divider.odd_0.out_counter ;
wire \divider.odd_0.out_counter2 ;
wire \divider.odd_0.rst_pulse ;
wire \divider.out ;
wire \divider.syncNp[0] ;
wire \divider.syncNp[1] ;
wire \divider.syncNp[2] ;
wire \divider2.even_0.N[0] ;
wire \divider2.even_0.N[1] ;
wire \divider2.even_0.N[2] ;
wire \divider2.even_0.counter[0] ;
wire \divider2.even_0.counter[1] ;
wire \divider2.even_0.counter[2] ;
wire \divider2.even_0.out_counter ;
wire \divider2.odd_0.counter2[0] ;
wire \divider2.odd_0.counter2[1] ;
wire \divider2.odd_0.counter2[2] ;
wire \divider2.odd_0.counter[0] ;
wire \divider2.odd_0.counter[1] ;
wire \divider2.odd_0.counter[2] ;
wire \divider2.odd_0.initial_begin[0] ;
wire \divider2.odd_0.initial_begin[1] ;
wire \divider2.odd_0.initial_begin[2] ;
wire \divider2.odd_0.old_N[0] ;
wire \divider2.odd_0.old_N[1] ;
wire \divider2.odd_0.old_N[2] ;
wire \divider2.odd_0.out_counter ;
wire \divider2.odd_0.out_counter2 ;
wire \divider2.odd_0.rst_pulse ;
wire \divider2.out ;
wire \divider2.syncNp[0] ;
wire \divider2.syncNp[1] ;
wire \divider2.syncNp[2] ;
wire ext_clk_syncd;
wire ext_clk_syncd_pre;
wire net1;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19;
wire net2;
wire net20;
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
wire net27;
wire net28;
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
wire net29;
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
wire net3;
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
wire net30;
wire net31;
wire net32;
wire net33;
wire net34;
wire net35;
wire net36;
wire net37;
wire net38;
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
wire net4;
wire net5;
wire net6;
wire net7;
wire net8;
wire net9;
wire pll_clk_sel;
wire \reset_delay[0] ;
wire \reset_delay[1] ;
wire \reset_delay[2] ;
wire use_pll_first;
wire use_pll_second;
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__283__A2 (.DIODE(net26),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__322__A (.DIODE(net26),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__323__B_N (.DIODE(net26),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__347__S (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__349__B (.DIODE(net26),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__421__A1 (.DIODE(net26),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__422__A1 (.DIODE(net26),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__425__A1 (.DIODE(net26),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__439__D (.DIODE(net26),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__445__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__446__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__447__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__448__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__449__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__450__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__451__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__452__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__453__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__454__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__455__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__456__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__457__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__458__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__459__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__460__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__461__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__462__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__463__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__464__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__465__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__466__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__467__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__468__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__469__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__470__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__471__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__472__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__473__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__474__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__475__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__476__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__477__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__478__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__479__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__480__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__481__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__482__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__483__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__484__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__485__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__486__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__487__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__488__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__489__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__490__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__491__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__492__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__493__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__494__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_ext_clk_A (.DIODE(ext_clk),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_pll_clk90_A (.DIODE(pll_clk90),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_pll_clk_A (.DIODE(pll_clk),
.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input1_A (.DIODE(ext_clk_sel),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input2_A (.DIODE(ext_reset),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input3_A (.DIODE(resetb),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input4_A (.DIODE(sel2[0]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input5_A (.DIODE(sel2[1]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input6_A (.DIODE(sel2[2]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input7_A (.DIODE(sel[0]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input8_A (.DIODE(sel[1]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input9_A (.DIODE(sel[2]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_0_101 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_0_105 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_0_11 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_113 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_0_122 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_131 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_142 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_0_144 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_157 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_0_165 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_0_17 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_0_170 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_0_189 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_0_196 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_25 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_0_29 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_0_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_0_40 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_0_61 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_0_66 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_0_83 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_10_116 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_10_118 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_10_141 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_10_151 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_10_166 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_10_170 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_10_196 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_10_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_10_37 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_10_40 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_10_7 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_10_73 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_10_92 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_11_101 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_11_105 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_11_117 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_11_125 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_11_131 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_11_143 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_155 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_157 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_11_193 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_201 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_25 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_11_30 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_42 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_11_49 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_11_53 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_11_75 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_11_79 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_12_11 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_116 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_12_139 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_12_14 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_12_144 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_152 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_159 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_196 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_12_3 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_38 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_12_40 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_12_59 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_7 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_92 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_13_101 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_13_105 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_13_126 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_13_138 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_13_146 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_13_15 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_13_180 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_13_19 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_13_190 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_13_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_13_34 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_13_49 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_13_61 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_13_68 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_14_11 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_116 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_14_132 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_142 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_14_146 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_170 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_14_196 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_14_3 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_14_36 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_14_40 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_14_52 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_14_89 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_14_92 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_113 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_146 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_160 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_15_192 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_196 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_15_53 (.VGND(VGND),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_15_59 (.VGND(VGND),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_70 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_15_79 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_16_104 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_16_127 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_16_142 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_16_165 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_16_196 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_16_3 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_16_34 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_16_38 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_16_40 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_16_50 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_16_62 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_16_66 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_16_78 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_16_88 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_16_9 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_17_102 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_17_105 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_17_135 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_17_157 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_17_181 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_17_191 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_17_199 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_17_47 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_17_51 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_17_75 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_17_79 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_18_138 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_18_165 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_18_170 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_196 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_3 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_38 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_18_45 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_18_57 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_18_87 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_9 (.VGND(VGND),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_94 (.VGND(VGND),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 FILLER_19_101 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_19_105 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_19_11 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_19_112 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_116 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_19_120 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_19_128 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_19_14 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_19_140 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_144 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_19_154 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_160 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_19_166 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_19_178 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_19_188 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_192 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_20 (.VGND(VGND),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_19_24 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_19_27 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_19_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_19_47 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_51 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_19_53 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_66 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_19_72 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_19_82 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_1_127 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_1_148 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_155 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_25 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_1_45 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_49 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_77 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_2_10 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_2_115 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_2_125 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_131 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_2_141 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_2_147 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_151 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_2_170 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_2_196 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_2_3 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_38 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_2_42 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_50 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_2_60 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_82 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_3_12 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_3_131 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_3_137 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_3_147 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_3_166 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_3_172 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_3_199 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_3_20 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_3_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_3_77 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_3_95 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_3_99 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_4_100 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_4_107 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_4_11 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_4_115 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_4_118 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_4_131 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_4_14 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_4_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_34 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_4_47 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_57 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_7 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_4_83 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_92 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_103 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_5_108 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_5_120 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_5_197 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_201 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_25 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_51 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_5_76 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_5_83 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_5_99 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_6_11 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_6_113 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_6_125 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_131 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_6_137 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_168 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_6_17 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_196 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_25 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_6_28 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_6_3 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_6_37 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_56 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_64 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_6_66 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_6_78 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_84 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_7_105 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_7_125 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_7_129 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_7_131 (.VGND(VGND),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_7_155 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_7_187 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_7_200 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_7_27 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_7_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_7_50 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_7_53 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_7_67 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_7_75 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_7_82 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_7_90 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_7_98 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_8_12 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_8_127 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_8_131 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_8_170 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_8_3 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_8_37 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_8_55 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_8_90 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_8_92 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_9_103 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_9_14 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_9_151 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_9_18 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_12 FILLER_9_190 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_9_3 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_6 FILLER_9_43 (.VGND(VGND),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_9_62 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_4 FILLER_9_68 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_9_72 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_1 FILLER_9_77 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_8 FILLER_9_79 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__decap_3 FILLER_9_87 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__fill_2 FILLER_9_97 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_32 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_33 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_38 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_39 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_100 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_101 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_102 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_103 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_104 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_105 (.VGND(VGND),
.VPWR(VPWR));
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_106 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_107 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_108 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_109 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_110 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_111 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VPWR(VPWR));
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_112 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VPWR(VPWR));
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_113 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VPWR(VPWR));
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_114 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_115 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_116 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VPWR(VPWR));
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_117 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_118 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_119 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_120 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_121 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_122 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_123 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_124 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_125 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_126 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_127 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_128 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_129 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_130 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_131 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_132 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_133 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_134 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_135 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_136 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_137 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_138 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_139 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_140 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_141 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_142 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_143 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_144 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_145 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_146 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_147 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_148 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_149 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_150 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_151 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_152 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_153 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_154 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_155 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_156 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_157 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_158 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_159 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_160 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_161 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_162 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_163 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_164 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_165 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_166 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_167 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_168 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_169 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_170 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_171 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_172 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_173 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_174 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_175 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_176 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_177 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_178 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_179 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_180 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_181 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_182 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_183 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_184 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_185 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_186 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_187 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_188 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_189 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_190 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_191 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_192 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_193 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_194 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_195 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_196 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_197 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_198 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_199 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_200 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_201 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_202 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_203 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_204 (.VGND(VGND),
.VPWR(VPWR));
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_40 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_41 (.VGND(VGND),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_42 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_43 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_44 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_45 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_46 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_47 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_48 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_49 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_50 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_51 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_52 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_53 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_54 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_55 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_56 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_57 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_58 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_59 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_60 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_61 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_62 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_63 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_64 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_65 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_66 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_67 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_68 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_69 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_70 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_71 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_72 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_73 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_74 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_75 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_76 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_77 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_78 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_79 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_80 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_81 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_82 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_83 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_84 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_85 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_86 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_87 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_88 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_89 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_90 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_91 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_92 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_93 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_94 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_95 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_96 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_97 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_98 (.VGND(VGND),
.VPWR(VPWR));
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_99 (.VGND(VGND),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _216_ (.A0(_016_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.counter[1] ),
.S(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_121_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_1 _217_ (.A(_121_),
.X(_119_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _218_ (.A0(_015_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.counter[0] ),
.S(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_122_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_1 _219_ (.A(_122_),
.X(_118_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__or2b_1 _220_ (.A(\divider2.even_0.N[1] ),
.B_N(\divider2.odd_0.old_N[1] ),
.X(_123_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__or2b_1 _221_ (.A(\divider2.odd_0.old_N[1] ),
.B_N(\divider2.even_0.N[1] ),
.X(_124_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _222_ (.A(_123_),
.B(_124_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider2.odd_0.old_N[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_125_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _223_ (.A(\divider2.even_0.N[2] ),
.B(\divider2.odd_0.old_N[2] ),
.Y(_126_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__and2_1 _224_ (.A(\divider2.even_0.N[2] ),
.B(\divider2.odd_0.old_N[2] ),
.X(_127_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21a_1 _225_ (.A1(\divider2.even_0.N[2] ),
.A2(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B1(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_128_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21ai_1 _226_ (.A1(_126_),
.A2(_127_),
.B1(_128_),
.Y(_129_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21ai_1 _227_ (.A1(\divider2.even_0.N[2] ),
.A2(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B1(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_130_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_4 _228_ (.A(\divider2.odd_0.rst_pulse ),
.Y(_131_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_2 _229_ (.A(_130_),
.B(_131_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_000_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21a_1 _230_ (.A1(_125_),
.A2(_129_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B1(_000_),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_117_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _231_ (.A(\divider2.odd_0.counter[2] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B(\divider2.odd_0.counter[1] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_132_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _232_ (.A(_132_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B(\divider2.odd_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_133_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_2 _233_ (.A(\divider2.odd_0.out_counter ),
.Y(_134_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3b_1 _234_ (.A_N(_133_),
.B(_134_),
.C(_128_),
.Y(_135_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_2 _235_ (.A(_131_),
.X(_136_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_2 _236_ (.A(_130_),
.X(_137_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21bai_1 _237_ (.A1(_137_),
.A2(_133_),
.B1_N(_134_),
.Y(_138_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _238_ (.A(_135_),
.B(_136_),
.C(_138_),
.Y(_116_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _239_ (.A(_137_),
.B(_136_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider2.odd_0.counter[2] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_139_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__a21bo_1 _240_ (.A1(_022_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(_000_),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.B1_N(_139_),
.X(_115_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _241_ (.A(_137_),
.B(_131_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider2.odd_0.counter[1] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_140_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__a21bo_1 _242_ (.A1(_021_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(_000_),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.B1_N(_140_),
.X(_114_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _243_ (.A(_137_),
.B(_131_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider2.odd_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_141_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__a21bo_1 _244_ (.A1(_020_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(_000_),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.B1_N(_141_),
.X(_113_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _245_ (.A0(\divider2.odd_0.initial_begin[2] ),
.A1(_025_),
.S(_002_),
.X(_142_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_1 _246_ (.A(_142_),
.X(_112_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_4 _247__1 (.A(clknet_1_0_0_pll_clk90),
.Y(net14),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _248_ (.A0(\divider2.odd_0.initial_begin[1] ),
.A1(_024_),
.S(_002_),
.X(_143_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_1 _249_ (.A(_143_),
.X(_111_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _250_ (.A0(\divider2.odd_0.initial_begin[0] ),
.A1(_023_),
.S(_002_),
.X(_144_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_1 _251_ (.A(_144_),
.X(_110_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_4 _252__2 (.A(clknet_1_0_0_pll_clk90),
.Y(net15),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _253_ (.A(\divider2.odd_0.initial_begin[2] ),
.B(\divider2.odd_0.initial_begin[1] ),
.Y(_145_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o211a_1 _254_ (.A1(\divider2.even_0.N[2] ),
.A2(\divider2.even_0.N[1] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B1(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.C1(_145_),
.X(_033_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_2 _255_ (.A(\divider2.odd_0.out_counter2 ),
.Y(_146_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor3b_2 _256_ (.A(\divider2.odd_0.counter2[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.counter2[1] ),
.C_N(\divider2.odd_0.counter2[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_034_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _257_ (.A(_033_),
.B(_146_),
.C(_034_),
.Y(_147_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _258_ (.A(\divider2.odd_0.counter2[2] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B(\divider2.odd_0.counter2[1] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_148_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _259_ (.A(_148_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B(\divider2.odd_0.counter2[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_149_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o211ai_4 _260_ (.A1(\divider2.even_0.N[2] ),
.A2(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B1(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.C1(_145_),
.Y(_150_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21bai_1 _261_ (.A1(_149_),
.A2(_150_),
.B1_N(_146_),
.Y(_151_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _262_ (.A(_147_),
.B(_151_),
.C(_136_),
.Y(_109_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _263_ (.A(_150_),
.B(_131_),
.Y(_152_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _264_ (.A(_152_),
.B(_019_),
.Y(_153_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _265_ (.A(_150_),
.B(_136_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.C(\divider2.odd_0.counter2[2] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_154_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _266_ (.A(_153_),
.B(_154_),
.Y(_108_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_4 _267__3 (.A(clknet_1_0_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(net16),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _268_ (.A(_152_),
.B(_018_),
.Y(_155_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _269_ (.A(_150_),
.B(_136_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.C(\divider2.odd_0.counter2[1] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_156_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _270_ (.A(_155_),
.B(_156_),
.Y(_107_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_2 _271_ (.A(\divider2.odd_0.counter2[0] ),
.Y(_065_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _272_ (.A(_152_),
.B(_017_),
.Y(_157_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21ai_1 _273_ (.A1(_065_),
.A2(_152_),
.B1(_157_),
.Y(_106_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor3b_2 _274_ (.A(\divider2.even_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.even_0.counter[2] ),
.C_N(\divider2.even_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_032_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_4 _275_ (.A(\divider2.even_0.N[0] ),
.Y(_158_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_4 _276_ (.A(\divider2.even_0.out_counter ),
.Y(_159_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__a21o_1 _277_ (.A1(_032_),
.A2(_158_),
.B1(_159_),
.X(_160_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _278_ (.A(_032_),
.B(_158_),
.C(_159_),
.Y(_161_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _279_ (.A(_160_),
.B(_161_),
.Y(_105_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _280_ (.A(\divider.odd_0.counter[2] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B(\divider.odd_0.counter[1] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_162_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _281_ (.A(_162_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B(\divider.odd_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_163_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_2 _282_ (.A(\divider.odd_0.out_counter ),
.Y(_164_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21a_1 _283_ (.A1(net30),
.A2(net26),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B1(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_165_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3b_1 _284_ (.A_N(_163_),
.B(_164_),
.C(_165_),
.Y(_166_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_4 _285_ (.A(\divider.odd_0.rst_pulse ),
.Y(_167_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_2 _286_ (.A(_167_),
.X(_168_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21ai_1 _287_ (.A1(\divider.even_0.N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(\divider.even_0.N[1] ),
.B1(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_169_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_2 _288_ (.A(_169_),
.X(_170_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21bai_1 _289_ (.A1(_170_),
.A2(_163_),
.B1_N(_164_),
.Y(_171_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _290_ (.A(_166_),
.B(_168_),
.C(_171_),
.Y(_104_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_2 _291_ (.A(_169_),
.B(_167_),
.Y(_001_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _292_ (.A(_170_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter[2] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.C(_168_),
.Y(_172_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__a21bo_1 _293_ (.A1(_011_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A2(_001_),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.B1_N(_172_),
.X(_103_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _294_ (.A(_170_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter[1] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.C(_167_),
.Y(_173_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__a21bo_1 _295_ (.A1(_010_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A2(_001_),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.B1_N(_173_),
.X(_102_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _296_ (.A(_170_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.C(_167_),
.Y(_174_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__a21bo_1 _297_ (.A1(_009_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A2(_001_),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.B1_N(_174_),
.X(_101_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _298_ (.A0(\divider.odd_0.initial_begin[2] ),
.A1(_014_),
.S(_003_),
.X(_175_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_1 _299_ (.A(_175_),
.X(_100_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_4 _300__4 (.A(clknet_1_0_0_pll_clk),
.Y(net17),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _301_ (.A0(\divider.odd_0.initial_begin[1] ),
.A1(_013_),
.S(_003_),
.X(_176_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_1 _302_ (.A(_176_),
.X(_099_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _303_ (.A0(\divider.odd_0.initial_begin[0] ),
.A1(_012_),
.S(_003_),
.X(_177_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_1 _304_ (.A(_177_),
.X(_098_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_4 _305__5 (.A(clknet_1_1_0_pll_clk),
.Y(net18),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _306_ (.A(\divider.odd_0.initial_begin[2] ),
.B(\divider.odd_0.initial_begin[1] ),
.Y(_178_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o211a_1 _307_ (.A1(\divider.even_0.N[2] ),
.A2(\divider.even_0.N[1] ),
.B1(\divider.even_0.N[0] ),
.C1(_178_),
.X(_029_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_2 _308_ (.A(\divider.odd_0.out_counter2 ),
.Y(_179_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor3b_2 _309_ (.A(\divider.odd_0.counter2[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter2[1] ),
.C_N(\divider.odd_0.counter2[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_030_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _310_ (.A(net38),
.B(_179_),
.C(_030_),
.Y(_180_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _311_ (.A(\divider.odd_0.counter2[2] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B(\divider.odd_0.counter2[1] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_181_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _312_ (.A(_181_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B(\divider.odd_0.counter2[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_182_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o211ai_4 _313_ (.A1(net27),
.A2(net28),
.B1(net32),
.C1(_178_),
.Y(_183_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21bai_1 _314_ (.A1(_182_),
.A2(_183_),
.B1_N(_179_),
.Y(_184_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _315_ (.A(_180_),
.B(_184_),
.C(_168_),
.Y(_097_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor3_1 _316_ (.A(\divider.even_0.N[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.even_0.counter[1] ),
.C(\divider.even_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_185_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xor2_1 _317_ (.A(\divider.even_0.counter[2] ),
.B(_185_),
.X(_096_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _318_ (.A0(_005_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.counter[1] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.S(net34),
.X(_186_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_1 _319_ (.A(_186_),
.X(_095_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _320_ (.A0(_004_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.S(net34),
.X(_187_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_1 _321_ (.A(_187_),
.X(_094_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__or2b_1 _322_ (.A(net26),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B_N(\divider.odd_0.old_N[1] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_188_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__or2b_1 _323_ (.A(\divider.odd_0.old_N[1] ),
.B_N(net26),
.X(_189_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _324_ (.A(_188_),
.B(_189_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider.odd_0.old_N[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_190_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _325_ (.A(net30),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.old_N[2] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_191_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__and2_1 _326_ (.A(net30),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.old_N[2] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_192_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21ai_1 _327_ (.A1(_191_),
.A2(_192_),
.B1(_165_),
.Y(_193_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21a_1 _328_ (.A1(_190_),
.A2(_193_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.B1(_001_),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_093_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _329_ (.A(_183_),
.B(_167_),
.Y(_194_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _330_ (.A(_194_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B(_008_),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_195_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _331_ (.A(_183_),
.B(_168_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.C(\divider.odd_0.counter2[2] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_196_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _332_ (.A(_195_),
.B(_196_),
.Y(_092_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_4 _333__6 (.A(clknet_1_1_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(net19),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _334_ (.A(_194_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(_007_),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_197_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand3_1 _335_ (.A(_183_),
.B(_168_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.C(\divider.odd_0.counter2[1] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_198_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _336_ (.A(_197_),
.B(_198_),
.Y(_091_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_2 _337_ (.A(\divider.odd_0.counter2[0] ),
.Y(_045_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nand2_1 _338_ (.A(_194_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(_006_),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_199_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21ai_1 _339_ (.A1(_045_),
.A2(_194_),
.B1(_199_),
.Y(_090_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _340_ (.A(\divider.even_0.counter[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.even_0.counter[1] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_200_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_4 _341_ (.A(net31),
.Y(_201_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__nand3_1 _342_ (.A(_200_),
.B(_201_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider.even_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_202_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xnor2_1 _343_ (.A(\divider.even_0.out_counter ),
.B(_202_),
.Y(_089_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_4 _344__9 (.A(net10),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(net22),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_4 _345__8 (.A(net10),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(net21),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__inv_4 _346__7 (.A(net10),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(net20),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_2 _347_ (.A0(ext_clk_syncd_pre),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(clknet_1_0_0_ext_clk),
.S(net3),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_203_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__buf_1 _348_ (.A(_203_),
.X(_088_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _349_ (.A(net30),
.B(net26),
.Y(_026_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _350_ (.A(\divider2.even_0.N[2] ),
.B(\divider2.even_0.N[1] ),
.Y(_027_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor3b_1 _351_ (.A(\divider.even_0.counter[2] ),
.B(\divider.even_0.counter[1] ),
.C_N(\divider.even_0.counter[0] ),
.Y(_028_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_4 _352_ (.A(_163_),
.Y(_031_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_4 _353_ (.A(_133_),
.Y(_035_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xnor2_1 _354_ (.A(\divider.odd_0.out_counter ),
.B(\divider.odd_0.out_counter2 ),
.Y(_204_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o2bb2ai_2 _355_ (.A1_N(_201_),
.A2_N(_036_),
.B1(_170_),
.B2(_204_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xnor2_1 _356_ (.A(\divider2.odd_0.out_counter ),
.B(\divider2.odd_0.out_counter2 ),
.Y(_205_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o2bb2ai_2 _357_ (.A1_N(_158_),
.A2_N(_038_),
.B1(_137_),
.B2(_205_),
.Y(\divider2.out ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_2 _358_ (.A(\divider.odd_0.initial_begin[0] ),
.Y(_039_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__xnor2_1 _359_ (.A(net33),
.B(net29),
.Y(_040_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xnor2_1 _360_ (.A(\divider.odd_0.initial_begin[1] ),
.B(\divider.odd_0.initial_begin[0] ),
.Y(_041_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__nor3_1 _361_ (.A(net33),
.B(\divider.even_0.N[2] ),
.C(net29),
.Y(_206_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__o21a_1 _362_ (.A1(net33),
.A2(net29),
.B1(\divider.even_0.N[2] ),
.X(_044_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__nor2_1 _363_ (.A(_206_),
.B(_044_),
.Y(_042_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__nor2_1 _364_ (.A(\divider.odd_0.initial_begin[1] ),
.B(\divider.odd_0.initial_begin[0] ),
.Y(_207_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__xor2_1 _365_ (.A(\divider.odd_0.initial_begin[2] ),
.B(_207_),
.X(_043_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__xnor2_1 _366_ (.A(\divider.odd_0.counter2[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter2[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_047_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _367_ (.A(\divider.odd_0.counter2[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter2[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_208_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xor2_1 _368_ (.A(\divider.odd_0.counter2[2] ),
.B(_208_),
.X(_049_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_2 _369_ (.A(\divider.odd_0.counter[0] ),
.Y(_051_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xnor2_1 _370_ (.A(\divider.odd_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_053_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _371_ (.A(\divider.odd_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_209_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xor2_1 _372_ (.A(\divider.odd_0.counter[2] ),
.B(_209_),
.X(_055_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_2 _373_ (.A(\divider.even_0.counter[0] ),
.Y(_057_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xnor2_1 _374_ (.A(\divider.even_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.even_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_058_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_2 _375_ (.A(\divider2.odd_0.initial_begin[0] ),
.Y(_059_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__xnor2_1 _376_ (.A(\divider2.even_0.N[0] ),
.B(\divider2.even_0.N[1] ),
.Y(_060_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__xnor2_1 _377_ (.A(\divider2.odd_0.initial_begin[1] ),
.B(\divider2.odd_0.initial_begin[0] ),
.Y(_061_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__nor3_1 _378_ (.A(\divider2.even_0.N[0] ),
.B(\divider2.even_0.N[2] ),
.C(\divider2.even_0.N[1] ),
.Y(_210_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__o21a_1 _379_ (.A1(\divider2.even_0.N[0] ),
.A2(\divider2.even_0.N[1] ),
.B1(\divider2.even_0.N[2] ),
.X(_064_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__nor2_1 _380_ (.A(_210_),
.B(_064_),
.Y(_062_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__nor2_1 _381_ (.A(\divider2.odd_0.initial_begin[1] ),
.B(\divider2.odd_0.initial_begin[0] ),
.Y(_211_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__xor2_1 _382_ (.A(\divider2.odd_0.initial_begin[2] ),
.B(_211_),
.X(_063_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__xnor2_1 _383_ (.A(\divider2.odd_0.counter2[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.counter2[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_067_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _384_ (.A(\divider2.odd_0.counter2[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.counter2[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_212_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xor2_1 _385_ (.A(\divider2.odd_0.counter2[2] ),
.B(_212_),
.X(_069_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_2 _386_ (.A(\divider2.odd_0.counter[0] ),
.Y(_071_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xnor2_1 _387_ (.A(\divider2.odd_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_073_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _388_ (.A(\divider2.odd_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_213_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xor2_1 _389_ (.A(\divider2.odd_0.counter[2] ),
.B(_213_),
.X(_075_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_2 _390_ (.A(\divider2.even_0.counter[0] ),
.Y(_077_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xnor2_1 _391_ (.A(\divider2.even_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.even_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_078_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkinv_4 _392_ (.A(net1),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(pll_clk_sel),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor2_1 _393_ (.A(net2),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\reset_delay[0] ),
.Y(net11),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__nor3_1 _394_ (.A(\divider2.even_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.even_0.N[0] ),
.C(\divider2.even_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.Y(_214_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__xor2_1 _395_ (.A(\divider2.even_0.counter[2] ),
.B(_214_),
.X(_120_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__conb_1 _396__13 (.LO(net13),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _397_ (.A0(_000_),
.A1(\divider2.odd_0.rst_pulse ),
.S(_033_),
.X(_002_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_2 _398_ (.A0(_001_),
.A1(\divider.odd_0.rst_pulse ),
.S(_029_),
.X(_003_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _399_ (.A0(_037_),
.A1(\divider.out ),
.S(use_pll_second),
.X(net10),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _400_ (.A0(_037_),
.A1(\divider2.out ),
.S(use_pll_second),
.X(net12),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _401_ (.A0(_065_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.S(_034_),
.X(_066_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _402_ (.A0(_066_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[0] ),
.S(\divider2.odd_0.rst_pulse ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_017_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _403_ (.A0(_067_),
.A1(\divider2.even_0.N[1] ),
.S(_034_),
.X(_068_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _404_ (.A0(_068_),
.A1(\divider2.even_0.N[1] ),
.S(\divider2.odd_0.rst_pulse ),
.X(_018_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _405_ (.A0(_073_),
.A1(\divider2.even_0.N[1] ),
.S(_035_),
.X(_074_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__mux2_1 _406_ (.A0(_074_),
.A1(\divider2.even_0.N[1] ),
.S(\divider2.odd_0.rst_pulse ),
.X(_021_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _407_ (.A0(_075_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[2] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.S(_035_),
.X(_076_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _408_ (.A0(_076_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[2] ),
.S(\divider2.odd_0.rst_pulse ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_022_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _409_ (.A0(_077_),
.A1(\divider2.even_0.N[1] ),
.S(_032_),
.X(_015_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _410_ (.A0(_039_),
.A1(_040_),
.S(\divider.odd_0.rst_pulse ),
.X(_012_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _411_ (.A0(_041_),
.A1(_042_),
.S(\divider.odd_0.rst_pulse ),
.X(_013_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _412_ (.A0(_043_),
.A1(_044_),
.S(\divider.odd_0.rst_pulse ),
.X(_014_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _413_ (.A0(_045_),
.A1(\divider.even_0.N[0] ),
.S(_030_),
.X(_046_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _414_ (.A0(_046_),
.A1(\divider.even_0.N[0] ),
.S(\divider.odd_0.rst_pulse ),
.X(_006_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _415_ (.A0(_047_),
.A1(\divider.even_0.N[1] ),
.S(_030_),
.X(_048_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _416_ (.A0(_048_),
.A1(\divider.even_0.N[1] ),
.S(\divider.odd_0.rst_pulse ),
.X(_007_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _417_ (.A0(_049_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.N[2] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.S(_030_),
.X(_050_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _418_ (.A0(_050_),
.A1(net37),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.S(\divider.odd_0.rst_pulse ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_008_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _419_ (.A0(_051_),
.A1(net35),
.S(_031_),
.X(_052_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__mux2_1 _420_ (.A0(_052_),
.A1(net36),
.S(\divider.odd_0.rst_pulse ),
.X(_009_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _421_ (.A0(_053_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.A1(net26),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.S(_031_),
.X(_054_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _422_ (.A0(_054_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.A1(net26),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.S(\divider.odd_0.rst_pulse ),
.X(_010_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _423_ (.A0(_055_),
.A1(net37),
.S(_031_),
.X(_056_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__mux2_1 _424_ (.A0(_056_),
.A1(net30),
.S(\divider.odd_0.rst_pulse ),
.X(_011_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__mux2_1 _425_ (.A0(_057_),
.A1(net26),
.S(_028_),
.X(_004_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__mux2_1 _426_ (.A0(_058_),
.A1(net30),
.S(_028_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.X(_005_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _427_ (.A0(_059_),
.A1(_060_),
.S(\divider2.odd_0.rst_pulse ),
.X(_023_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _428_ (.A0(_061_),
.A1(_062_),
.S(\divider2.odd_0.rst_pulse ),
.X(_024_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _429_ (.A0(_063_),
.A1(_064_),
.S(\divider2.odd_0.rst_pulse ),
.X(_025_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _430_ (.A0(_069_),
.A1(\divider2.even_0.N[2] ),
.S(_034_),
.X(_070_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _431_ (.A0(_070_),
.A1(\divider2.even_0.N[2] ),
.S(\divider2.odd_0.rst_pulse ),
.X(_019_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _432_ (.A0(_071_),
.A1(\divider2.even_0.N[0] ),
.S(_035_),
.X(_072_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__mux2_1 _433_ (.A0(_072_),
.A1(\divider2.even_0.N[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.S(\divider2.odd_0.rst_pulse ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_020_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _434_ (.A0(_078_),
.A1(\divider2.even_0.N[2] ),
.S(_032_),
.X(_016_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _435_ (.A0(\divider.even_0.out_counter ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(clknet_1_1_0_pll_clk),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.S(_026_),
.X(_036_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _436_ (.A0(clknet_1_1_0_ext_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(ext_clk_syncd),
.S(use_pll_first),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.X(_037_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__mux2_1 _437_ (.A0(\divider2.even_0.out_counter ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(clknet_1_1_0_pll_clk90),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.S(_027_),
.X(_038_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfxtp_1 _438_ (.D(\divider.even_0.N[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.old_N[0] ),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfxtp_1 _439_ (.D(net26),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.old_N[1] ),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfxtp_1 _440_ (.D(net30),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.old_N[2] ),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.CLK(clknet_1_1_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfxtp_1 _441_ (.D(\divider2.even_0.N[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.old_N[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_1_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfxtp_1 _442_ (.D(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.old_N[1] ),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.CLK(clknet_1_0_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfxtp_1 _443_ (.D(\divider2.even_0.N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.old_N[2] ),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.CLK(clknet_1_1_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfxtp_1 _444_ (.D(_088_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(ext_clk_syncd_pre),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _445_ (.D(net25),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\reset_delay[0] ),
.SET_B(net3),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.CLK(net20),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _446_ (.D(net24),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\reset_delay[1] ),
.SET_B(net3),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.CLK(net21),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _447_ (.D(net13),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\reset_delay[2] ),
.SET_B(net3),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.CLK(net22),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _448_ (.D(pll_clk_sel),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(use_pll_first),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _449_ (.D(use_pll_first),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(use_pll_second),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _450_ (.D(net23),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(ext_clk_syncd),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _451_ (.D(net7),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.syncNp[0] ),
.RESET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _452_ (.D(net8),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.syncNp[1] ),
.SET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _453_ (.D(net9),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.syncNp[2] ),
.RESET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_4 _454_ (.D(\divider.syncNp[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.N[0] ),
.RESET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_4 _455_ (.D(\divider.syncNp[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.N[1] ),
.SET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_4 _456_ (.D(\divider.syncNp[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.N[2] ),
.RESET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _457_ (.D(net4),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.syncNp[0] ),
.RESET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _458_ (.D(net5),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.syncNp[1] ),
.SET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _459_ (.D(net6),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.syncNp[2] ),
.RESET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_4 _460_ (.D(\divider2.syncNp[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.N[0] ),
.RESET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_4 _461_ (.D(\divider2.syncNp[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.N[1] ),
.SET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_4 _462_ (.D(\divider2.syncNp[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.N[2] ),
.RESET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _463_ (.D(_089_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.out_counter ),
.SET_B(net3),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.CLK(clknet_1_1_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtn_1 _464_ (.D(_090_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter2[0] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK_N(clknet_1_1_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _465_ (.D(_091_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter2[1] ),
.SET_B(net3),
.CLK(net19),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtn_1 _466_ (.D(_092_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter2[2] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK_N(clknet_1_1_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_4 _467_ (.D(_093_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.rst_pulse ),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_2 _468_ (.D(_094_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.counter[0] ),
.SET_B(net3),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_2 _469_ (.D(_095_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.counter[1] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _470_ (.D(_096_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.counter[2] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _471_ (.D(_097_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.out_counter2 ),
.SET_B(net3),
.CLK(net18),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtn_1 _472_ (.D(_098_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.initial_begin[0] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _473_ (.D(_099_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.initial_begin[1] ),
.SET_B(net3),
.CLK(net17),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtn_1 _474_ (.D(_100_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.initial_begin[2] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_2 _475_ (.D(_101_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter[0] ),
.RESET_B(net3),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.CLK(clknet_1_1_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _476_ (.D(_102_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter[1] ),
.SET_B(net3),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _477_ (.D(_103_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter[2] ),
.RESET_B(net3),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _478_ (.D(_104_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.out_counter ),
.SET_B(net3),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _479_ (.D(_105_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.out_counter ),
.SET_B(net3),
.CLK(clknet_1_1_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtn_1 _480_ (.D(_106_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter2[0] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _481_ (.D(_107_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter2[1] ),
.SET_B(net3),
.CLK(net16),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtn_1 _482_ (.D(_108_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter2[2] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _483_ (.D(_109_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.out_counter2 ),
.SET_B(net3),
.CLK(net15),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtn_1 _484_ (.D(_110_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.initial_begin[0] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _485_ (.D(_111_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.initial_begin[1] ),
.SET_B(net3),
.CLK(net14),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtn_1 _486_ (.D(_112_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.initial_begin[2] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_2 _487_ (.D(_113_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter[0] ),
.RESET_B(net3),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.CLK(clknet_1_1_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _488_ (.D(_114_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter[1] ),
.SET_B(net3),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.CLK(clknet_1_0_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _489_ (.D(_115_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter[2] ),
.RESET_B(net3),
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
.CLK(clknet_1_0_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _490_ (.D(_116_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.out_counter ),
.SET_B(net3),
.CLK(clknet_1_1_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_4 _491_ (.D(_117_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.rst_pulse ),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfstp_1 _492_ (.D(_118_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.counter[0] ),
.SET_B(net3),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.CLK(clknet_1_1_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _493_ (.D(_119_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.counter[1] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.CLK(clknet_1_1_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dfrtp_1 _494_ (.D(_120_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.counter[2] ),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_16 clkbuf_0_ext_clk (.A(ext_clk),
.X(clknet_0_ext_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_16 clkbuf_0_pll_clk (.A(pll_clk),
.X(clknet_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_16 clkbuf_0_pll_clk90 (.A(pll_clk90),
.X(clknet_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_ext_clk (.A(clknet_0_ext_clk),
.X(clknet_1_0_0_ext_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_pll_clk (.A(clknet_0_pll_clk),
.X(clknet_1_0_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_pll_clk90 (.A(clknet_0_pll_clk90),
.X(clknet_1_0_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_ext_clk (.A(clknet_0_ext_clk),
.X(clknet_1_1_0_ext_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_pll_clk (.A(clknet_0_pll_clk),
.X(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_pll_clk90 (.A(clknet_0_pll_clk90),
.X(clknet_1_1_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold1 (.A(ext_clk_syncd_pre),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(net23),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkdlybuf4s25_1 hold2 (.A(\reset_delay[2] ),
.X(net24),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold3 (.A(\reset_delay[1] ),
.X(net25),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dlymetal6s2s_1 input1 (.A(ext_clk_sel),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.X(net1),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input2 (.A(ext_reset),
.X(net2),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__buf_12 input3 (.A(resetb),
.X(net3),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input4 (.A(sel2[0]),
.X(net4),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input5 (.A(sel2[1]),
.X(net5),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input6 (.A(sel2[2]),
.X(net6),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input7 (.A(sel[0]),
.X(net7),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input8 (.A(sel[1]),
.X(net8),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input9 (.A(sel[2]),
.X(net9),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 output10 (.A(net10),
.X(core_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__buf_2 output11 (.A(net11),
.X(resetb_sync),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 output12 (.A(net12),
.X(user_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_1 rebuffer10 (.A(\divider.even_0.N[0] ),
.X(net32),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 rebuffer11 (.A(\divider.even_0.N[0] ),
.X(net33),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__dlygate4sd1_1 rebuffer12 (.A(net33),
.X(net34),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__dlygate4sd1_1 rebuffer13 (.A(\divider.even_0.N[0] ),
.X(net35),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__dlygate4sd1_1 rebuffer14 (.A(net35),
.X(net36),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__dlygate4sd1_1 rebuffer16 (.A(_029_),
.X(net38),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 rebuffer5 (.A(net37),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(net27),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__dlygate4sd1_1 rebuffer6 (.A(\divider.even_0.N[1] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(net28),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__clkbuf_2 rebuffer7 (.A(\divider.even_0.N[1] ),
.X(net29),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 rebuffer9 (.A(\divider.even_0.N[0] ),
.X(net31),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 split15 (.A(\divider.even_0.N[2] ),
.X(net37),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_4 split4 (.A(\divider.even_0.N[1] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(net26),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-07 05:36:56 -06:00
sky130_fd_sc_hd__buf_2 split8 (.A(net37),
.X(net30),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
endmodule