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caravel
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caravel/verilog/gl/caravel_clocking.v

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[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
module caravel_clocking (VGND,
VPWR,
core_clk,
ext_clk,
ext_clk_sel,
ext_reset,
pll_clk,
pll_clk90,
resetb,
resetb_sync,
user_clk,
sel,
sel2);
input VGND;
input VPWR;
output core_clk;
input ext_clk;
input ext_clk_sel;
input ext_reset;
input pll_clk;
input pll_clk90;
input resetb;
output resetb_sync;
output user_clk;
input [2:0] sel;
input [2:0] sel2;
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire clknet_0_ext_clk;
wire clknet_0_pll_clk;
wire clknet_0_pll_clk90;
wire clknet_1_0_0_ext_clk;
wire clknet_1_0_0_pll_clk;
wire clknet_1_0_0_pll_clk90;
wire clknet_1_1_0_ext_clk;
wire clknet_1_1_0_pll_clk;
wire clknet_1_1_0_pll_clk90;
wire \divider.even_0.N[0] ;
wire \divider.even_0.N[1] ;
wire \divider.even_0.N[2] ;
wire \divider.even_0.counter[0] ;
wire \divider.even_0.counter[1] ;
wire \divider.even_0.counter[2] ;
wire \divider.even_0.out_counter ;
wire \divider.odd_0.counter2[0] ;
wire \divider.odd_0.counter2[1] ;
wire \divider.odd_0.counter2[2] ;
wire \divider.odd_0.counter[0] ;
wire \divider.odd_0.counter[1] ;
wire \divider.odd_0.counter[2] ;
wire \divider.odd_0.initial_begin[0] ;
wire \divider.odd_0.initial_begin[1] ;
wire \divider.odd_0.initial_begin[2] ;
wire \divider.odd_0.old_N[0] ;
wire \divider.odd_0.old_N[1] ;
wire \divider.odd_0.old_N[2] ;
wire \divider.odd_0.out_counter ;
wire \divider.odd_0.out_counter2 ;
wire \divider.odd_0.rst_pulse ;
wire \divider.out ;
wire \divider.syncNp[0] ;
wire \divider.syncNp[1] ;
wire \divider.syncNp[2] ;
wire \divider2.even_0.N[0] ;
wire \divider2.even_0.N[1] ;
wire \divider2.even_0.N[2] ;
wire \divider2.even_0.counter[0] ;
wire \divider2.even_0.counter[1] ;
wire \divider2.even_0.counter[2] ;
wire \divider2.even_0.out_counter ;
wire \divider2.odd_0.counter2[0] ;
wire \divider2.odd_0.counter2[1] ;
wire \divider2.odd_0.counter2[2] ;
wire \divider2.odd_0.counter[0] ;
wire \divider2.odd_0.counter[1] ;
wire \divider2.odd_0.counter[2] ;
wire \divider2.odd_0.initial_begin[0] ;
wire \divider2.odd_0.initial_begin[1] ;
wire \divider2.odd_0.initial_begin[2] ;
wire \divider2.odd_0.old_N[0] ;
wire \divider2.odd_0.old_N[1] ;
wire \divider2.odd_0.old_N[2] ;
wire \divider2.odd_0.out_counter ;
wire \divider2.odd_0.out_counter2 ;
wire \divider2.odd_0.rst_pulse ;
wire \divider2.out ;
wire \divider2.syncNp[0] ;
wire \divider2.syncNp[1] ;
wire \divider2.syncNp[2] ;
wire ext_clk_syncd;
wire ext_clk_syncd_pre;
wire net1;
wire net10;
wire net11;
wire net12;
wire net13;
wire net14;
wire net15;
wire net16;
wire net17;
wire net18;
wire net19;
wire net2;
wire net20;
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
wire net21;
wire net22;
wire net23;
wire net24;
wire net25;
wire net26;
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
wire net27;
wire net28;
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
wire net3;
wire net4;
wire net5;
wire net6;
wire net7;
wire net8;
wire net9;
wire pll_clk_sel;
wire \reset_delay[0] ;
wire \reset_delay[1] ;
wire \reset_delay[2] ;
wire use_pll_first;
wire use_pll_second;
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__274__B1 (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__278__B1 (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__310__B1 (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__313__A (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__315__S (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__317__S (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__338__A_N (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__343__S (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__350__A_N (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__385__A1 (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__386__A1 (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__404__A1 (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__405__A1 (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__414__D (.DIODE(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__421__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__422__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__423__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__424__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__425__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__426__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__427__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__428__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__429__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__430__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__431__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__432__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__433__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__434__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__435__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__436__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__437__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__438__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__439__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__440__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__441__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__442__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__443__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__444__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__445__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__446__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__447__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__448__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__449__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__450__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__451__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__452__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__453__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__454__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__455__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__456__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__457__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__458__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__459__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__460__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__461__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__462__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__463__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__464__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__465__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__466__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__467__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__468__SET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__469__RESET_B (.DIODE(net3),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__470__RESET_B (.DIODE(net3),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_ext_clk_A (.DIODE(ext_clk),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_pll_clk90_A (.DIODE(pll_clk90),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_pll_clk_A (.DIODE(pll_clk),
.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input1_A (.DIODE(ext_clk_sel),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input2_A (.DIODE(ext_reset),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input3_A (.DIODE(resetb),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input4_A (.DIODE(sel2[0]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input5_A (.DIODE(sel2[1]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input6_A (.DIODE(sel2[2]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input7_A (.DIODE(sel[0]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input8_A (.DIODE(sel[1]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA_input9_A (.DIODE(sel[2]),
.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_103 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_0_105 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_0_11 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_0_118 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_0_135 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_0_14 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_0_150 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_0_157 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_0_180 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_0_190 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_194 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_0_196 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_0_27 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_0_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_0_40 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_0_53 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_57 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_0_69 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_77 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_0_79 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_0_92 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_98 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_10_11 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_10_125 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_10_137 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_10_14 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_10_144 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_10_152 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_10_161 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_10_170 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_10_200 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_10_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_10_32 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_10_92 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_11_125 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_151 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_11_174 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_178 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_201 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_25 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_27 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_11_46 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_11_66 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_11_79 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_83 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_12_11 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_116 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_12_134 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_12_139 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_12_14 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_12_170 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_196 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_22 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_12_25 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_12_3 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_12_40 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_60 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_66 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_13_101 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_13_105 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_13_131 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_13_143 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_13_178 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_13_183 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_13_195 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_13_201 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_13_31 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_13_39 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_13_43 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_13_53 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_13_68 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_13_76 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_13_79 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_13_89 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_14_11 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_14_115 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_14_118 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_122 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_14_14 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_14_144 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_148 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_14_166 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_18 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_14_196 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_22 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_14_3 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_14_37 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_14_40 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_14_52 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_56 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_14_61 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_14_74 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_78 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_84 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_15_105 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_15_134 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_15_148 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_155 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_15_157 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_15_183 (.VGND(VGND),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_15_195 (.VGND(VGND),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_31 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_15_50 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_79 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_83 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_15_88 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_16_11 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_16_114 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_16_139 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_16_170 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_16_196 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_16_3 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_16_35 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_16_40 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_16_53 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_16_63 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_16_66 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_16_90 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_16_92 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_17_102 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_17_105 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_17_131 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_17_157 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_17_191 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_17_199 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_17_40 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_17_50 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_17_53 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_17_60 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_17_72 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_2 FILLER_18_11 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_142 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_144 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_18_166 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_196 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__decap_8 FILLER_18_3 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_35 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_18_56 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_64 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_4 FILLER_18_87 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 FILLER_19_101 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_2 FILLER_19_11 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_19_116 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_19_127 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_14 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_19_140 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_155 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_2 FILLER_19_160 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_19_167 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_19_178 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_19_188 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_192 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_19_20 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_19_27 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_19_3 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_19_37 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_19_47 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_19_51 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_19_53 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_19_66 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_19_86 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_1_114 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_1_122 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_129 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
sky130_fd_sc_hd__decap_8 FILLER_1_15 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_157 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_1_183 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_1_194 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_23 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_1_85 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_97 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
sky130_fd_sc_hd__fill_2 FILLER_2_11 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_2_113 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_2_138 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_2_14 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_142 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_144 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_2_148 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_156 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_170 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_18 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_2_196 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_2_3 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_48 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_2_66 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_90 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_3_102 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_3_111 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_3_117 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_3_125 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_3_131 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_3_157 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_3_192 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_3_200 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_3_25 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_3_41 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_3_53 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__decap_4 FILLER_3_62 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_3_84 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_3_92 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_4_11 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_4_127 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_4_139 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_4_14 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_4_144 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_4_156 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_196 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_4_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_2 FILLER_4_37 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_4_40 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_7 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_4_70 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_4_80 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_88 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_103 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_112 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_5_119 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_181 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__decap_12 FILLER_5_183 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__decap_6 FILLER_5_195 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_201 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_25 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_27 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_5_44 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_5_53 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_5_94 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_5_99 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_6_107 (.VGND(VGND),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_6_115 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_12 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_6_127 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_6_14 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_166 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_170 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_6_200 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_6_28 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_6_3 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_32 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_38 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_6_40 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_6_52 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_60 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_6_66 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_77 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_6_80 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_6_88 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_7_114 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_7_120 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_7_124 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_7_131 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_7_137 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_7_148 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_7_183 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_7_195 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_7_46 (.VGND(VGND),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_7_74 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_7_88 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_8_103 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_8_11 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_8_115 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_8_14 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_8_168 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_6 FILLER_8_196 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_8_26 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_8_3 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_8_30 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_8_38 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_8_61 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_8_81 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_8_89 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_8_92 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_2 FILLER_9_102 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_9_107 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_9_118 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_9_126 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__decap_4 FILLER_9_151 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__fill_1 FILLER_9_155 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
sky130_fd_sc_hd__decap_3 FILLER_9_157 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_12 FILLER_9_183 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_9_195 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_9_29 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_9_3 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_9_33 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__fill_1 FILLER_9_37 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_2 FILLER_9_40 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_9_44 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_8 FILLER_9_53 (.VGND(VGND),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_3 FILLER_9_61 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_9_66 (.VGND(VGND),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__decap_4 FILLER_9_74 (.VGND(VGND),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__fill_1 FILLER_9_79 (.VGND(VGND),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_32 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_33 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_38 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_39 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_100 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_101 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_102 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_103 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_104 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_105 (.VGND(VGND),
.VPWR(VPWR));
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_106 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_107 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_108 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_109 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_110 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_111 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VPWR(VPWR));
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_112 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VPWR(VPWR));
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_113 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VPWR(VPWR));
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_114 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_115 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_116 (.VGND(VGND),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.VPWR(VPWR));
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_117 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_118 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_119 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_120 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_121 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_122 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_123 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_124 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_125 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_126 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_127 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_128 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_129 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_130 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_131 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_132 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_133 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_134 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_135 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_136 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_137 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_138 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_139 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_140 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_141 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_142 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_143 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_144 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_145 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_146 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_147 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_148 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_149 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_150 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_151 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_152 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_153 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_154 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_155 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_156 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_157 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_158 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_159 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_160 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_161 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_162 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_163 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_164 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_165 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_166 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_167 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_168 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_169 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_170 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_171 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_172 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_173 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_174 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_175 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_176 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_177 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_178 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_179 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_180 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_181 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_182 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_183 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_184 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_185 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_186 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_187 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_188 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_189 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_190 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_191 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_192 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_193 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_194 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_195 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_196 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_197 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_198 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_199 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_200 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_201 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_202 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_203 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_204 (.VGND(VGND),
.VPWR(VPWR));
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_40 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_41 (.VGND(VGND),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_42 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_43 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_44 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_45 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_46 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_47 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_48 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_49 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_50 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_51 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_52 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_53 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_54 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_55 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_56 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_57 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_58 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_59 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_60 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_61 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_62 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_63 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_64 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_65 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_66 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_67 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_68 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_69 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_70 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_71 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_72 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_73 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_74 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_75 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_76 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_77 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_78 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_79 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_80 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_81 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_82 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_83 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_84 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_85 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_86 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_87 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_88 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_89 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_90 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_91 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_92 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_93 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_94 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_95 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_96 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_97 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_98 (.VGND(VGND),
.VPWR(VPWR));
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_99 (.VGND(VGND),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _204_ (.A0(_013_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.counter[1] ),
.S(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_090_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkbuf_1 _205_ (.A(_090_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_088_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _206_ (.A0(_012_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.counter[0] ),
.S(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_091_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkbuf_1 _207_ (.A(_091_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_087_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__or2b_1 _208_ (.A(\divider2.odd_0.old_N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B_N(\divider2.even_0.N[1] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_092_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__or2b_1 _209_ (.A(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B_N(\divider2.odd_0.old_N[1] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_093_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _210_ (.A(_092_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.B(_093_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider2.odd_0.old_N[0] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_094_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _211_ (.A(\divider2.odd_0.old_N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.even_0.N[2] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_095_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__and2_1 _212_ (.A(\divider2.odd_0.old_N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.even_0.N[2] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_096_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21a_1 _213_ (.A1(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(\divider2.even_0.N[2] ),
.B1(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_097_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21ai_1 _214_ (.A1(_095_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A2(_096_),
.B1(_097_),
.Y(_098_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21ai_1 _215_ (.A1(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(\divider2.even_0.N[2] ),
.B1(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_099_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_4 _216_ (.A(\divider2.odd_0.rst_pulse ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_100_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_2 _217_ (.A(_099_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.B(_100_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_000_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21a_1 _218_ (.A1(_094_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A2(_098_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B1(_000_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_086_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _219_ (.A(\divider2.odd_0.counter[2] ),
.B(\divider2.odd_0.counter[1] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_101_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _220_ (.A(_101_),
.B(\divider2.odd_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_102_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_2 _221_ (.A(\divider2.odd_0.out_counter ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_103_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3b_1 _222_ (.A_N(_102_),
.B(_103_),
.C(_097_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_104_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkbuf_2 _223_ (.A(_100_),
.X(_105_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkbuf_2 _224_ (.A(_099_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_106_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21bai_1 _225_ (.A1(_106_),
.A2(_102_),
.B1_N(_103_),
.Y(_107_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _226_ (.A(_104_),
.B(_105_),
.C(_107_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_085_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _227_ (.A(_106_),
.B(_105_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider2.odd_0.counter[2] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_108_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__a21bo_1 _228_ (.A1(_019_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(_000_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B1_N(_108_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_084_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _229_ (.A(_106_),
.B(_100_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider2.odd_0.counter[1] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_109_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__a21bo_1 _230_ (.A1(_018_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(_000_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B1_N(_109_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_083_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _231_ (.A(_106_),
.B(_100_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider2.odd_0.counter[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_110_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__a21bo_1 _232_ (.A1(_017_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(_000_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B1_N(_110_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_082_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor3b_1 _233_ (.A(\divider2.odd_0.rst_pulse ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.initial_begin[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.C_N(_002_),
.Y(_111_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_2 _234_ (.A(\divider2.odd_0.initial_begin[2] ),
.B(\divider2.odd_0.initial_begin[1] ),
.Y(_112_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _235_ (.A(\divider2.odd_0.initial_begin[1] ),
.B(\divider2.odd_0.initial_begin[0] ),
.Y(_113_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_2 _236_ (.A(_002_),
.Y(_114_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21bai_1 _237_ (.A1(\divider2.odd_0.rst_pulse ),
.A2(_113_),
.B1_N(_114_),
.Y(_115_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__a22o_1 _238_ (.A1(_111_),
.A2(_112_),
.B1(_115_),
.B2(\divider2.odd_0.initial_begin[2] ),
.X(_081_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_4 _239__1 (.A(clknet_1_0_0_pll_clk90),
.Y(net14),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_2 _240_ (.A(\divider2.odd_0.initial_begin[1] ),
.Y(_116_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__and2b_1 _241_ (.A_N(\divider2.odd_0.initial_begin[0] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.B(_002_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_117_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21ai_1 _242_ (.A1(_116_),
.A2(_117_),
.B1(_115_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_080_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__a21o_1 _243_ (.A1(_114_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(\divider2.odd_0.initial_begin[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B1(_111_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_079_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_4 _244__2 (.A(clknet_1_0_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(net15),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o211a_1 _245_ (.A1(\divider2.even_0.N[1] ),
.A2(\divider2.even_0.N[2] ),
.B1(\divider2.even_0.N[0] ),
.C1(_112_),
.X(_027_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_4 _246_ (.A(\divider2.odd_0.out_counter2 ),
.Y(_118_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor3b_2 _247_ (.A(\divider2.odd_0.counter2[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.counter2[1] ),
.C_N(\divider2.odd_0.counter2[0] ),
.Y(_028_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _248_ (.A(_027_),
.B(_118_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(_028_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_119_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _249_ (.A(\divider2.odd_0.counter2[2] ),
.B(\divider2.odd_0.counter2[1] ),
.Y(_120_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _250_ (.A(_120_),
.B(\divider2.odd_0.counter2[0] ),
.Y(_121_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o211ai_4 _251_ (.A1(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(\divider2.even_0.N[2] ),
.B1(\divider2.even_0.N[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.C1(_112_),
.Y(_122_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21bai_1 _252_ (.A1(_121_),
.A2(_122_),
.B1_N(_118_),
.Y(_123_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _253_ (.A(_119_),
.B(_123_),
.C(_105_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_078_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _254_ (.A(_122_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.B(_100_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_124_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _255_ (.A(_124_),
.B(_016_),
.Y(_125_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _256_ (.A(_122_),
.B(_105_),
.C(\divider2.odd_0.counter2[2] ),
.Y(_126_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _257_ (.A(_125_),
.B(_126_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_077_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_4 _258__3 (.A(clknet_1_0_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(net16),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _259_ (.A(_124_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(_015_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_127_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__nand3_1 _260_ (.A(_122_),
.B(_105_),
.C(\divider2.odd_0.counter2[1] ),
.Y(_128_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _261_ (.A(_127_),
.B(_128_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_076_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_2 _262_ (.A(\divider2.odd_0.counter2[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_040_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _263_ (.A(_124_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(_014_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_129_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21ai_1 _264_ (.A1(_040_),
.A2(_124_),
.B1(_129_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_075_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor3b_2 _265_ (.A(\divider2.even_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.even_0.counter[2] ),
.C_N(\divider2.even_0.counter[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_130_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_4 _266_ (.A(\divider2.even_0.N[0] ),
.Y(_131_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_2 _267_ (.A(\divider2.even_0.out_counter ),
.Y(_132_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__a21o_1 _268_ (.A1(_130_),
.A2(_131_),
.B1(_132_),
.X(_133_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _269_ (.A(_130_),
.B(_131_),
.C(_132_),
.Y(_134_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _270_ (.A(_133_),
.B(_134_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_074_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _271_ (.A(\divider.odd_0.counter[2] ),
.B(\divider.odd_0.counter[1] ),
.Y(_135_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _272_ (.A(_135_),
.B(\divider.odd_0.counter[0] ),
.Y(_136_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_2 _273_ (.A(\divider.odd_0.out_counter ),
.Y(_137_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21a_1 _274_ (.A1(\divider.even_0.N[2] ),
.A2(\divider.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B1(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_138_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3b_1 _275_ (.A_N(_136_),
.B(_137_),
.C(_138_),
.Y(_139_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_2 _276_ (.A(\divider.odd_0.rst_pulse ),
.Y(_140_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkbuf_2 _277_ (.A(_140_),
.X(_141_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21ai_2 _278_ (.A1(\divider.even_0.N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(\divider.even_0.N[1] ),
.B1(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_142_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkbuf_2 _279_ (.A(_142_),
.X(_143_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21bai_1 _280_ (.A1(_143_),
.A2(_136_),
.B1_N(_137_),
.Y(_144_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _281_ (.A(_139_),
.B(_141_),
.C(_144_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_073_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkbuf_2 _282_ (.A(_140_),
.X(_145_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__nand2_2 _283_ (.A(_142_),
.B(_145_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_001_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _284_ (.A(_143_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter[2] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.C(_141_),
.Y(_146_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__a21bo_1 _285_ (.A1(_011_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A2(_001_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B1_N(_146_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_072_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _286_ (.A(_143_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter[1] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.C(_145_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_147_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__a21bo_1 _287_ (.A1(_010_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A2(_001_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B1_N(_147_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_071_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _288_ (.A(_143_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter[0] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.C(_145_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_148_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__a21bo_1 _289_ (.A1(_009_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A2(_001_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B1_N(_148_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_070_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _290_ (.A(\divider.odd_0.initial_begin[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.initial_begin[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_149_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_2 _291_ (.A(net28),
.Y(_150_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21bai_1 _292_ (.A1(\divider.odd_0.rst_pulse ),
.A2(_149_),
.B1_N(_150_),
.Y(_151_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3b_1 _293_ (.A_N(\divider.odd_0.initial_begin[0] ),
.B(_145_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(_003_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_152_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_2 _294_ (.A(\divider.odd_0.initial_begin[2] ),
.Y(_153_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_4 _295_ (.A(\divider.odd_0.initial_begin[1] ),
.Y(_154_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _296_ (.A(_153_),
.B(_154_),
.Y(_155_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o2bb2ai_1 _297_ (.A1_N(\divider.odd_0.initial_begin[2] ),
.A2_N(_151_),
.B1(_152_),
.B2(_155_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_069_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_4 _298__4 (.A(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(net17),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__and2b_1 _299_ (.A_N(\divider.odd_0.initial_begin[0] ),
.B(net28),
.X(_156_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21ai_1 _300_ (.A1(_154_),
.A2(_156_),
.B1(_151_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_068_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__a21bo_1 _301_ (.A1(_150_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2(\divider.odd_0.initial_begin[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B1_N(_152_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_067_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_4 _302__5 (.A(clknet_1_1_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(net18),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _303_ (.A(_142_),
.B(_155_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_023_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_2 _304_ (.A(\divider.odd_0.out_counter2 ),
.Y(_157_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor3b_4 _305_ (.A(\divider.odd_0.counter2[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter2[1] ),
.C_N(\divider.odd_0.counter2[0] ),
.Y(_024_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _306_ (.A(net27),
.B(_157_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(_024_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_158_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _307_ (.A(\divider.odd_0.counter2[2] ),
.B(\divider.odd_0.counter2[1] ),
.Y(_159_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _308_ (.A(_159_),
.B(\divider.odd_0.counter2[0] ),
.Y(_160_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _309_ (.A(\divider.odd_0.initial_begin[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.initial_begin[1] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_161_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o211ai_2 _310_ (.A1(\divider.even_0.N[2] ),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A2(\divider.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B1(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.C1(_161_),
.Y(_162_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21bai_1 _311_ (.A1(_160_),
.A2(_162_),
.B1_N(_157_),
.Y(_163_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _312_ (.A(_158_),
.B(_163_),
.C(_141_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_066_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor3_1 _313_ (.A(\divider.even_0.N[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.even_0.counter[1] ),
.C(\divider.even_0.counter[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_164_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xor2_1 _314_ (.A(\divider.even_0.counter[2] ),
.B(_164_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_065_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _315_ (.A0(_005_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.counter[1] ),
.S(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_165_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkbuf_1 _316_ (.A(_165_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_064_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _317_ (.A0(_004_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.counter[0] ),
.S(\divider.even_0.N[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_166_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkbuf_1 _318_ (.A(_166_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_063_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__or2b_1 _319_ (.A(net26),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B_N(\divider.odd_0.old_N[1] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_167_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__or2b_1 _320_ (.A(\divider.odd_0.old_N[1] ),
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 13:07:45 -06:00
.B_N(\divider.even_0.N[1] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_168_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _321_ (.A(_167_),
.B(_168_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider.odd_0.old_N[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_169_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _322_ (.A(\divider.even_0.N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.old_N[2] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_170_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__and2_1 _323_ (.A(\divider.even_0.N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.old_N[2] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_171_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21ai_1 _324_ (.A1(_170_),
.A2(_171_),
.B1(_138_),
.Y(_172_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21a_1 _325_ (.A1(_169_),
.A2(_172_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.B1(_001_),
.X(_062_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _326_ (.A(_162_),
.B(_145_),
.Y(_173_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _327_ (.A(_173_),
.B(_008_),
.Y(_174_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3_1 _328_ (.A(_162_),
.B(_141_),
.C(\divider.odd_0.counter2[2] ),
.Y(_175_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _329_ (.A(_174_),
.B(_175_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_061_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_4 _330__6 (.A(clknet_1_1_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(net19),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _331_ (.A(_173_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(_007_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_176_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__nand3_1 _332_ (.A(_162_),
.B(_141_),
.C(\divider.odd_0.counter2[1] ),
.Y(_177_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _333_ (.A(_176_),
.B(_177_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_060_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_2 _334_ (.A(\divider.odd_0.counter2[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_032_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _335_ (.A(_173_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(_006_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_178_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21ai_1 _336_ (.A1(_032_),
.A2(_173_),
.B1(_178_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_059_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _337_ (.A(\divider.even_0.counter[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.even_0.counter[1] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_179_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand3b_1 _338_ (.A_N(\divider.even_0.N[0] ),
.B(_179_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(\divider.even_0.counter[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_180_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xnor2_1 _339_ (.A(\divider.even_0.out_counter ),
.B(_180_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(_058_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_4 _340__9 (.A(net10),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(net22),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_4 _341__8 (.A(net10),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(net21),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__inv_4 _342__7 (.A(net10),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.Y(net20),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_2 _343_ (.A0(ext_clk_syncd_pre),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(clknet_1_0_0_ext_clk),
.S(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_181_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__buf_1 _344_ (.A(_181_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_057_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_4 _345_ (.A(_136_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_025_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_4 _346_ (.A(_130_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_026_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_4 _347_ (.A(_102_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_029_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _348_ (.A(\divider.even_0.N[2] ),
.B(net26),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_020_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xnor2_1 _349_ (.A(\divider.odd_0.out_counter ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.out_counter2 ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_182_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__and2b_2 _350_ (.A_N(\divider.even_0.N[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(_030_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_183_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o21bai_2 _351_ (.A1(_143_),
.A2(_182_),
.B1_N(_183_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _352_ (.A(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.even_0.N[2] ),
.Y(_021_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xnor2_1 _353_ (.A(\divider2.odd_0.out_counter ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.out_counter2 ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_184_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__o2bb2ai_2 _354_ (.A1_N(_131_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A2_N(_031_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.B1(_106_),
.B2(_184_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xnor2_1 _355_ (.A(\divider.odd_0.counter2[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter2[0] ),
.Y(_033_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _356_ (.A(\divider.odd_0.counter2[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter2[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_185_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xor2_1 _357_ (.A(\divider.odd_0.counter2[2] ),
.B(_185_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.X(_034_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_2 _358_ (.A(\divider.odd_0.counter[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_035_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xnor2_1 _359_ (.A(\divider.odd_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter[0] ),
.Y(_036_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _360_ (.A(\divider.odd_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.odd_0.counter[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_186_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xor2_1 _361_ (.A(\divider.odd_0.counter[2] ),
.B(_186_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.X(_037_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_2 _362_ (.A(\divider.even_0.counter[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_038_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xnor2_1 _363_ (.A(\divider.even_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.even_0.counter[0] ),
.Y(_039_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nand2_1 _364_ (.A(_179_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider.even_0.counter[0] ),
.Y(_022_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xnor2_1 _365_ (.A(\divider2.odd_0.counter2[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.counter2[0] ),
.Y(_041_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _366_ (.A(\divider2.odd_0.counter2[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.counter2[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_187_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xor2_1 _367_ (.A(\divider2.odd_0.counter2[2] ),
.B(_187_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.X(_042_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_2 _368_ (.A(\divider2.odd_0.counter[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_043_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xnor2_1 _369_ (.A(\divider2.odd_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.counter[0] ),
.Y(_044_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _370_ (.A(\divider2.odd_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.odd_0.counter[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_188_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xor2_1 _371_ (.A(\divider2.odd_0.counter[2] ),
.B(_188_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.X(_045_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_2 _372_ (.A(\divider2.even_0.counter[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_046_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xnor2_1 _373_ (.A(\divider2.even_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.even_0.counter[0] ),
.Y(_047_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkinv_4 _374_ (.A(net1),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(pll_clk_sel),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor2_1 _375_ (.A(net2),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\reset_delay[0] ),
.Y(net11),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__nor3_1 _376_ (.A(\divider2.even_0.counter[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B(\divider2.even_0.N[0] ),
.C(\divider2.even_0.counter[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.Y(_189_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__xor2_1 _377_ (.A(\divider2.even_0.counter[2] ),
.B(_189_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(_089_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__conb_1 _378__13 (.LO(net13),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _379_ (.A0(_043_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[0] ),
.S(_029_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_200_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _380_ (.A0(_200_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[0] ),
.S(\divider2.odd_0.rst_pulse ),
.X(_017_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _381_ (.A0(_033_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A1(\divider.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.S(_024_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_192_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _382_ (.A0(_192_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A1(\divider.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.S(\divider.odd_0.rst_pulse ),
.X(_007_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _383_ (.A0(_040_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[0] ),
.S(_028_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_197_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _384_ (.A0(_197_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[0] ),
.S(\divider2.odd_0.rst_pulse ),
.X(_014_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _385_ (.A0(_032_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.N[0] ),
.S(_024_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_191_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _386_ (.A0(_191_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.N[0] ),
.S(\divider.odd_0.rst_pulse ),
.X(_006_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _387_ (.A0(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(_046_),
.S(_026_),
.X(_012_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _388_ (.A0(_045_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[2] ),
.S(_029_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_202_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _389_ (.A0(_202_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[2] ),
.S(\divider2.odd_0.rst_pulse ),
.X(_019_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _390_ (.A0(_000_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.odd_0.rst_pulse ),
.S(_027_),
.X(_002_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _391_ (.A0(_044_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A1(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.S(_029_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_201_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _392_ (.A0(_201_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A1(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.S(\divider2.odd_0.rst_pulse ),
.X(_018_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _393_ (.A0(_190_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.out ),
.S(use_pll_second),
.X(net10),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _394_ (.A0(_190_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.out ),
.S(use_pll_second),
.X(net12),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _395_ (.A0(_042_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[2] ),
.S(_028_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_199_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _396_ (.A0(_199_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[2] ),
.S(\divider2.odd_0.rst_pulse ),
.X(_016_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_4 _397_ (.A0(_001_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.odd_0.rst_pulse ),
.S(_023_),
.X(_003_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _398_ (.A0(_037_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.N[2] ),
.S(_025_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_196_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _399_ (.A0(_196_),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.A1(\divider.even_0.N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.S(\divider.odd_0.rst_pulse ),
.X(_011_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _400_ (.A0(net26),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(_038_),
.S(_022_),
.X(_004_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _401_ (.A0(_036_),
.A1(net26),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.S(_025_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_195_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _402_ (.A0(_195_),
.A1(net26),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.S(\divider.odd_0.rst_pulse ),
.X(_010_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _403_ (.A0(\divider.even_0.N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(_039_),
.S(_022_),
.X(_005_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _404_ (.A0(_035_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.N[0] ),
.S(_025_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_194_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _405_ (.A0(_194_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.N[0] ),
.S(\divider.odd_0.rst_pulse ),
.X(_009_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _406_ (.A0(_034_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.N[2] ),
.S(_024_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_193_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _407_ (.A0(_193_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider.even_0.N[2] ),
.S(\divider.odd_0.rst_pulse ),
.X(_008_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _408_ (.A0(_041_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[1] ),
.S(_028_),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_198_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _409_ (.A0(_198_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(\divider2.even_0.N[1] ),
.S(\divider2.odd_0.rst_pulse ),
.X(_015_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _410_ (.A0(\divider2.even_0.N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(_047_),
.S(_026_),
.X(_013_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _411_ (.A0(\divider.even_0.out_counter ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(clknet_1_1_0_pll_clk),
.S(_020_),
.X(_030_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _412_ (.A0(clknet_1_1_0_ext_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(ext_clk_syncd),
.S(use_pll_first),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.X(_190_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__mux2_1 _413_ (.A0(\divider2.even_0.out_counter ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A1(clknet_1_1_0_pll_clk90),
.S(_021_),
.X(_031_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfxtp_1 _414_ (.D(\divider.even_0.N[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.old_N[0] ),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfxtp_1 _415_ (.D(net26),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.old_N[1] ),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfxtp_1 _416_ (.D(\divider.even_0.N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.old_N[2] ),
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
.CLK(clknet_1_1_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfxtp_1 _417_ (.D(\divider2.even_0.N[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.old_N[0] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_1_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfxtp_1 _418_ (.D(\divider2.even_0.N[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.old_N[1] ),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.CLK(clknet_1_0_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfxtp_1 _419_ (.D(\divider2.even_0.N[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.old_N[2] ),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_0_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfxtp_1 _420_ (.D(_057_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(ext_clk_syncd_pre),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _421_ (.D(net25),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\reset_delay[0] ),
.SET_B(net3),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.CLK(net20),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _422_ (.D(net24),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\reset_delay[1] ),
.SET_B(net3),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.CLK(net21),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _423_ (.D(net13),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\reset_delay[2] ),
.SET_B(net3),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.CLK(net22),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _424_ (.D(pll_clk_sel),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(use_pll_first),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _425_ (.D(use_pll_first),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(use_pll_second),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _426_ (.D(net23),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(ext_clk_syncd),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _427_ (.D(net7),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.syncNp[0] ),
.RESET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _428_ (.D(net8),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.syncNp[1] ),
.SET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _429_ (.D(net9),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.syncNp[2] ),
.RESET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_4 _430_ (.D(\divider.syncNp[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.N[0] ),
.RESET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_4 _431_ (.D(\divider.syncNp[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.N[1] ),
.SET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_4 _432_ (.D(\divider.syncNp[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.N[2] ),
.RESET_B(net3),
.CLK(\divider.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _433_ (.D(net4),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.syncNp[0] ),
.RESET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _434_ (.D(net5),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.syncNp[1] ),
.SET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _435_ (.D(net6),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.syncNp[2] ),
.RESET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_4 _436_ (.D(\divider2.syncNp[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.N[0] ),
.RESET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_4 _437_ (.D(\divider2.syncNp[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.N[1] ),
.SET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_4 _438_ (.D(\divider2.syncNp[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.N[2] ),
.RESET_B(net3),
.CLK(\divider2.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _439_ (.D(_058_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.out_counter ),
.SET_B(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtn_1 _440_ (.D(_059_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter2[0] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK_N(clknet_1_1_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_2 _441_ (.D(_060_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter2[1] ),
.SET_B(net3),
.CLK(net19),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtn_1 _442_ (.D(_061_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter2[2] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK_N(clknet_1_1_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_4 _443_ (.D(_062_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.rst_pulse ),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_2 _444_ (.D(_063_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.counter[0] ),
.SET_B(net3),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _445_ (.D(_064_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.counter[1] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _446_ (.D(_065_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.even_0.counter[2] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _447_ (.D(_066_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.out_counter2 ),
.SET_B(net3),
.CLK(net18),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtn_1 _448_ (.D(_067_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.initial_begin[0] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _449_ (.D(_068_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.initial_begin[1] ),
.SET_B(net3),
.CLK(net17),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtn_1 _450_ (.D(_069_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.initial_begin[2] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_2 _451_ (.D(_070_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter[0] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _452_ (.D(_071_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter[1] ),
.SET_B(net3),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _453_ (.D(_072_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.counter[2] ),
.RESET_B(net3),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.CLK(clknet_1_0_0_pll_clk),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _454_ (.D(_073_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider.odd_0.out_counter ),
.SET_B(net3),
.CLK(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _455_ (.D(_074_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.out_counter ),
.SET_B(net3),
.CLK(clknet_1_1_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtn_1 _456_ (.D(_075_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter2[0] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _457_ (.D(_076_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter2[1] ),
.SET_B(net3),
.CLK(net16),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtn_1 _458_ (.D(_077_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter2[2] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _459_ (.D(_078_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.out_counter2 ),
.SET_B(net3),
.CLK(net15),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtn_1 _460_ (.D(_079_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.initial_begin[0] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _461_ (.D(_080_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.initial_begin[1] ),
.SET_B(net3),
.CLK(net14),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtn_1 _462_ (.D(_081_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.initial_begin[2] ),
.RESET_B(net3),
.CLK_N(clknet_1_0_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_2 _463_ (.D(_082_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter[0] ),
.RESET_B(net3),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.CLK(clknet_1_0_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _464_ (.D(_083_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter[1] ),
.SET_B(net3),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.CLK(clknet_1_0_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _465_ (.D(_084_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.counter[2] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
.CLK(clknet_1_1_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _466_ (.D(_085_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.out_counter ),
.SET_B(net3),
.CLK(clknet_1_1_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_4 _467_ (.D(_086_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.odd_0.rst_pulse ),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfstp_1 _468_ (.D(_087_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.counter[0] ),
.SET_B(net3),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.CLK(clknet_1_1_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _469_ (.D(_088_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.counter[1] ),
.RESET_B(net3),
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
.CLK(clknet_1_1_0_pll_clk90),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dfrtp_1 _470_ (.D(_089_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Q(\divider2.even_0.counter[2] ),
.RESET_B(net3),
.CLK(clknet_1_1_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_16 clkbuf_0_ext_clk (.A(ext_clk),
.X(clknet_0_ext_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_16 clkbuf_0_pll_clk (.A(pll_clk),
.X(clknet_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_16 clkbuf_0_pll_clk90 (.A(pll_clk90),
.X(clknet_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_ext_clk (.A(clknet_0_ext_clk),
.X(clknet_1_0_0_ext_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_pll_clk (.A(clknet_0_pll_clk),
.X(clknet_1_0_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_pll_clk90 (.A(clknet_0_pll_clk90),
.X(clknet_1_0_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_ext_clk (.A(clknet_0_ext_clk),
.X(clknet_1_1_0_ext_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_pll_clk (.A(clknet_0_pll_clk),
.X(clknet_1_1_0_pll_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_pll_clk90 (.A(clknet_0_pll_clk90),
.X(clknet_1_1_0_pll_clk90),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold1 (.A(ext_clk_syncd_pre),
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
.X(net23),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkdlybuf4s25_1 hold2 (.A(\reset_delay[2] ),
.X(net24),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkdlybuf4s25_1 hold3 (.A(\reset_delay[1] ),
.X(net25),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
sky130_fd_sc_hd__clkbuf_1 input1 (.A(ext_clk_sel),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.X(net1),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input2 (.A(ext_reset),
.X(net2),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__buf_12 input3 (.A(resetb),
.X(net3),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input4 (.A(sel2[0]),
.X(net4),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input5 (.A(sel2[1]),
.X(net5),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input6 (.A(sel2[2]),
.X(net6),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input7 (.A(sel[0]),
.X(net7),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input8 (.A(sel[1]),
.X(net8),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 input9 (.A(sel[2]),
.X(net9),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 output10 (.A(net10),
.X(core_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__buf_2 output11 (.A(net11),
.X(resetb_sync),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 output12 (.A(net12),
.X(user_clk),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__dlygate4sd1_1 rebuffer5 (.A(_023_),
.X(net27),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__buf_2 rebuffer6 (.A(_003_),
.X(net28),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
sky130_fd_sc_hd__clkbuf_2 split4 (.A(\divider.even_0.N[1] ),
.X(net26),
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 07:23:01 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
endmodule