2021-10-12 15:31:42 -05:00
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// `default_nettype none
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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/*--------------------------------------------------------------*/
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/* caravan, a project harness for the Google/SkyWater sky130 */
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/* fabrication process and open source PDK. caravan is an */
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/* alternative architecture to caravel that has simple straight */
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/* through connections replacing the GPIO pads on the top side */
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/* of the padframe. A total of 11 pads are converted from GPIO */
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/* to analog, leaving 27 GPIO. */
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/* */
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/* Copyright 2021 efabless, Inc. */
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/* Written by Tim Edwards, December 2019 */
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/* and Mohamed Shalan, August 2020 */
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/* This file is open source hardware released under the */
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/* Apache 2.0 license. See file LICENSE. */
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/* */
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/*--------------------------------------------------------------*/
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/*--------------------------------------------------------------*/
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/* Derived types for the array bounds on the two digital and */
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/* two analog pad arrays. As defined above, the sections have */
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/* the number of pads as follows: */
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/* */
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/* DIG2 : 13 GPIO pads */
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/* ANA2 : 6 analog pads */
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/* ANA1 : 5 analog pads */
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/* DIG1 : 14 GPIO pads */
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/* */
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/* This makes a total of 38 pads = `MPRJ_IO_PADS */
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/* The pads are still designated as mprj_io[37:0] around the */
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/* padframe. The SoC core remains the same, so the programming */
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/* of the digital signals remains the same, but the values for */
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/* GPIO 15-25 are not used. */
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/*--------------------------------------------------------------*/
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`define DIG2_TOP (`MPRJ_IO_PADS - 1)
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`define DIG2_BOT (`MPRJ_IO_PADS_1 + `ANALOG_PADS_2)
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`define ANA2_TOP (`MPRJ_IO_PADS_1 + `ANALOG_PADS_2 - 1)
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`define ANA2_BOT (`MPRJ_IO_PADS_1)
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`define ANA1_TOP (`MPRJ_IO_PADS_1 - 1)
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`define ANA1_BOT (`MPRJ_IO_PADS_1 - `ANALOG_PADS_1)
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`define DIG1_TOP (`MPRJ_IO_PADS_1 - `ANALOG_PADS_1 - 1)
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`define DIG1_BOT (0)
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`define MPRJ_DIG_PADS (`MPRJ_IO_PADS - `ANALOG_PADS)
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/*--------------------------------------------------------------*/
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/*--------------------------------------------------------------*/
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module caravan (
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inout vddio, // Common 3.3V padframe/ESD power
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inout vddio_2, // Common 3.3V padframe/ESD power
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inout vssio, // Common padframe/ESD ground
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inout vssio_2, // Common padframe/ESD ground
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inout vdda, // Management 3.3V power
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inout vssa, // Common analog ground
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inout vccd, // Management/Common 1.8V power
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inout vssd, // Common digital ground
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inout vdda1, // User area 1 3.3V power
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inout vdda1_2, // User area 1 3.3V power
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inout vdda2, // User area 2 3.3V power
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inout vssa1, // User area 1 analog ground
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inout vssa1_2, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V power
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inout vccd2, // User area 2 1.8V power
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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inout gpio, // Used for external LDO control
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inout [`MPRJ_IO_PADS-1:0] mprj_io,
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input clock, // CMOS core clock input, not a crystal
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input resetb,
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// Note that only two pins are available on the flash so dual and
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// quad flash modes are not available.
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output flash_csb,
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output flash_clk,
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output flash_io0,
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output flash_io1
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);
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//------------------------------------------------------------
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// This value is uniquely defined for each user project.
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//------------------------------------------------------------
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parameter USER_PROJECT_ID = 32'h00000000;
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2021-10-25 14:08:13 -05:00
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/*
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*---------------------------------------------------------------------
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* These pins are overlaid on mprj_io space. They have the function
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* below when the management processor is in reset, or in the default
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* configuration. They are assigned to uses in the user space by the
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* configuration program running off of the SPI flash. Note that even
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* when the user has taken control of these pins, they can be restored
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* to the original use by setting the resetb pin low. The SPI pins and
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* UART pins can be connected directly to an FTDI chip as long as the
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* FTDI chip sets these lines to high impedence (input function) at
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* all times except when holding the chip in reset.
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*
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* JTAG = mprj_io[0] (inout)
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* SDO = mprj_io[1] (output)
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* SDI = mprj_io[2] (input)
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* CSB = mprj_io[3] (input)
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* SCK = mprj_io[4] (input)
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* ser_rx = mprj_io[5] (input)
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* ser_tx = mprj_io[6] (output)
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* irq = mprj_io[7] (input)
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*
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* spi_sck = mprj_io[32] (output)
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* spi_csb = mprj_io[33] (output)
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* spi_sdi = mprj_io[34] (input)
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* spi_sdo = mprj_io[35] (output)
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* flash_io2 = mprj_io[36] (inout)
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* flash_io3 = mprj_io[37] (inout)
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*
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* These pins are reserved for any project that wants to incorporate
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* its own processor and flash controller. While a user project can
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* technically use any available I/O pins for the purpose, these
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* four pins connect to a pass-through mode from the SPI slave (pins
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* 1-4 above) so that any SPI flash connected to these specific pins
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* can be accessed through the SPI slave even when the processor is in
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* reset.
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*
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* user_flash_csb = mprj_io[8]
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* user_flash_sck = mprj_io[9]
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* user_flash_io0 = mprj_io[10]
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* user_flash_io1 = mprj_io[11]
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*
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*---------------------------------------------------------------------
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*/
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2021-10-12 15:31:42 -05:00
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// One-bit GPIO dedicated to management SoC (outside of user control)
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wire gpio_out_core;
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wire gpio_in_core;
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wire gpio_mode0_core;
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wire gpio_mode1_core;
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wire gpio_outenb_core;
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wire gpio_inenb_core;
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// 27 GPIO pads with full controls
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_inp_dis;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_oeb;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_ib_mode_sel;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_vtrip_sel;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_slow_sel;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_holdover;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_en;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_sel;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_pol;
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wire [(`MPRJ_IO_PADS-`ANALOG_PADS)*3-1:0] mprj_io_dm;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in_3v3;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_out;
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// User Project Control (user-facing)
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// 27 GPIO bidirectional with in/out/oeb and a 3.3V copy of the input
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_oeb;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_in;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_out;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_in_3v3;
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// 18 direct connections to GPIO for low-frequency, low-voltage analog
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] user_gpio_analog;
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wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] user_gpio_noesd;
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// 3 power supply ESD clamps for user applications
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wire [2:0] user_clamp_high;
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wire [2:0] user_clamp_low;
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// 11 core connections to the analog pads
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wire [`ANALOG_PADS-1:0] user_analog;
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/* Padframe control signals */
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wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1:0] gpio_serial_link_1;
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wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:0] gpio_serial_link_2;
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wire mprj_io_loader_resetn;
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wire mprj_io_loader_clock;
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2021-11-03 22:18:36 -05:00
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wire mprj_io_loader_strobe;
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2021-10-12 15:31:42 -05:00
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wire mprj_io_loader_data_1; /* user1 side serial loader */
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wire mprj_io_loader_data_2; /* user2 side serial loader */
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// User Project Control management I/O
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// There are two types of GPIO connections:
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// (1) Full Bidirectional: Management connects to in, out, and oeb
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// Uses: JTAG and SDO
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// (2) Selectable bidirectional: Management connects to in and out,
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// which are tied together. oeb is grounded (oeb from the
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// configuration is used)
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// SDI = mprj_io[2] (input)
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// CSB = mprj_io[3] (input)
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// SCK = mprj_io[4] (input)
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// ser_rx = mprj_io[5] (input)
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// ser_tx = mprj_io[6] (output)
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// irq = mprj_io[7] (input)
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2021-10-25 14:08:13 -05:00
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wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data */
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wire [`MPRJ_IO_PADS-1:0] mgmt_io_nc; /* no-connects */
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wire [4:0] mgmt_io_out; /* three-pin interface out */
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wire [4:0] mgmt_io_oeb; /* three-pin output enable */
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2021-11-21 21:58:39 -06:00
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wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc; /* no-connects */
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2021-10-12 15:31:42 -05:00
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wire clock_core;
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// Power-on-reset signal. The reset pad generates the sense-inverted
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// reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
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// derived.
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wire porb_h;
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wire porb_l;
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wire por_l;
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wire rstb_h;
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wire rstb_l;
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2021-10-25 14:08:13 -05:00
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// Flash SPI communication (managment SoC to housekeeping)
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wire flash_clk_core, flash_csb_core;
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wire flash_clk_oeb_core, flash_csb_oeb_core;
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wire flash_clk_ieb_core, flash_csb_ieb_core;
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wire flash_io0_oeb_core, flash_io1_oeb_core;
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wire flash_io2_oeb_core, flash_io3_oeb_core;
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wire flash_io0_ieb_core, flash_io1_ieb_core;
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wire flash_io2_ieb_core, flash_io3_ieb_core;
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wire flash_io0_do_core, flash_io1_do_core;
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2021-10-25 14:08:13 -05:00
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wire flash_io2_do_core, flash_io3_do_core;
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2021-10-12 15:31:42 -05:00
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wire flash_io0_di_core, flash_io1_di_core;
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2021-10-25 14:08:13 -05:00
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wire flash_io2_di_core, flash_io3_di_core;
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// Flash SPI communication
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wire flash_clk_frame;
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wire flash_csb_frame;
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wire flash_clk_oeb, flash_csb_oeb;
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wire flash_clk_ieb, flash_csb_ieb;
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wire flash_io0_oeb, flash_io1_oeb;
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wire flash_io0_ieb, flash_io1_ieb;
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wire flash_io0_do, flash_io1_do;
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wire flash_io0_di, flash_io1_di;
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2021-10-12 15:31:42 -05:00
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chip_io_alt #(
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.ANALOG_PADS_1(`ANALOG_PADS_1),
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.ANALOG_PADS_2(`ANALOG_PADS_2)
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) padframe (
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`ifndef TOP_ROUTING
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// Package Pins
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.vddio_pad (vddio), // Common padframe/ESD supply
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.vddio_pad2 (vddio_2),
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.vssio_pad (vssio), // Common padframe/ESD ground
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.vssio_pad2 (vssio_2),
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.vccd_pad (vccd), // Common 1.8V supply
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.vssd_pad (vssd), // Common digital ground
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.vdda_pad (vdda), // Management analog 3.3V supply
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.vssa_pad (vssa), // Management analog ground
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.vdda1_pad (vdda1), // User area 1 3.3V supply
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.vdda1_pad2 (vdda1_2),
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.vdda2_pad (vdda2), // User area 2 3.3V supply
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.vssa1_pad (vssa1), // User area 1 analog ground
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.vssa1_pad2 (vssa1_2),
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.vssa2_pad (vssa2), // User area 2 analog ground
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.vccd1_pad (vccd1), // User area 1 1.8V supply
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.vccd2_pad (vccd2), // User area 2 1.8V supply
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.vssd1_pad (vssd1), // User area 1 digital ground
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.vssd2_pad (vssd2), // User area 2 digital ground
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`endif
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// Core Side Pins
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.vddio (vddio_core),
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.vssio (vssio_core),
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.vdda (vdda_core),
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.vssa (vssa_core),
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.vccd (vccd_core),
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.vssd (vssd_core),
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.vdda1 (vdda1_core),
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.vdda2 (vdda2_core),
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.vssa1 (vssa1_core),
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.vssa2 (vssa2_core),
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.vccd1 (vccd1_core),
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.vccd2 (vccd2_core),
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.vssd1 (vssd1_core),
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.vssd2 (vssd2_core),
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.gpio(gpio),
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.mprj_io(mprj_io),
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|
|
.clock(clock),
|
|
|
|
.resetb(resetb),
|
|
|
|
.flash_csb(flash_csb),
|
|
|
|
.flash_clk(flash_clk),
|
|
|
|
.flash_io0(flash_io0),
|
|
|
|
.flash_io1(flash_io1),
|
|
|
|
// SoC Core Interface
|
|
|
|
.porb_h(porb_h),
|
|
|
|
.por(por_l),
|
|
|
|
.resetb_core_h(rstb_h),
|
|
|
|
.clock_core(clock_core),
|
|
|
|
.gpio_out_core(gpio_out_core),
|
|
|
|
.gpio_in_core(gpio_in_core),
|
|
|
|
.gpio_mode0_core(gpio_mode0_core),
|
|
|
|
.gpio_mode1_core(gpio_mode1_core),
|
|
|
|
.gpio_outenb_core(gpio_outenb_core),
|
|
|
|
.gpio_inenb_core(gpio_inenb_core),
|
2021-10-25 14:08:13 -05:00
|
|
|
.flash_csb_core(flash_csb_frame),
|
|
|
|
.flash_clk_core(flash_clk_frame),
|
|
|
|
.flash_csb_oeb_core(flash_csb_oeb),
|
|
|
|
.flash_clk_oeb_core(flash_clk_oeb),
|
|
|
|
.flash_io0_oeb_core(flash_io0_oeb),
|
|
|
|
.flash_io1_oeb_core(flash_io1_oeb),
|
|
|
|
.flash_csb_ieb_core(flash_csb_ieb),
|
|
|
|
.flash_clk_ieb_core(flash_clk_ieb),
|
|
|
|
.flash_io0_ieb_core(flash_io0_ieb),
|
|
|
|
.flash_io1_ieb_core(flash_io1_ieb),
|
|
|
|
.flash_io0_do_core(flash_io0_do),
|
|
|
|
.flash_io1_do_core(flash_io1_do),
|
|
|
|
.flash_io0_di_core(flash_io0_di),
|
|
|
|
.flash_io1_di_core(flash_io1_di),
|
2021-10-12 15:31:42 -05:00
|
|
|
.mprj_io_in(mprj_io_in),
|
|
|
|
.mprj_io_in_3v3(mprj_io_in_3v3),
|
|
|
|
.mprj_io_out(mprj_io_out),
|
|
|
|
.mprj_io_oeb(mprj_io_oeb),
|
|
|
|
.mprj_io_inp_dis(mprj_io_inp_dis),
|
|
|
|
.mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
|
|
|
|
.mprj_io_vtrip_sel(mprj_io_vtrip_sel),
|
|
|
|
.mprj_io_slow_sel(mprj_io_slow_sel),
|
|
|
|
.mprj_io_holdover(mprj_io_holdover),
|
|
|
|
.mprj_io_analog_en(mprj_io_analog_en),
|
|
|
|
.mprj_io_analog_sel(mprj_io_analog_sel),
|
|
|
|
.mprj_io_analog_pol(mprj_io_analog_pol),
|
|
|
|
.mprj_io_dm(mprj_io_dm),
|
|
|
|
.mprj_gpio_analog(user_gpio_analog),
|
|
|
|
.mprj_gpio_noesd(user_gpio_noesd),
|
|
|
|
.mprj_analog(user_analog),
|
|
|
|
.mprj_clamp_high(user_clamp_high),
|
|
|
|
.mprj_clamp_low(user_clamp_low)
|
|
|
|
);
|
|
|
|
|
|
|
|
// SoC core
|
|
|
|
wire caravel_clk;
|
|
|
|
wire caravel_clk2;
|
|
|
|
wire caravel_rstn;
|
|
|
|
|
|
|
|
wire [7:0] spi_ro_config_core;
|
|
|
|
|
|
|
|
// LA signals
|
|
|
|
wire [127:0] la_data_in_user; // From CPU to MPRJ
|
|
|
|
wire [127:0] la_data_in_mprj; // From MPRJ to CPU
|
|
|
|
wire [127:0] la_data_out_mprj; // From CPU to MPRJ
|
|
|
|
wire [127:0] la_data_out_user; // From MPRJ to CPU
|
|
|
|
wire [127:0] la_oenb_user; // From CPU to MPRJ
|
|
|
|
wire [127:0] la_oenb_mprj; // From CPU to MPRJ
|
|
|
|
wire [127:0] la_iena_mprj; // From CPU only
|
|
|
|
|
|
|
|
wire [2:0] user_irq; // From MPRJ to CPU
|
|
|
|
wire [2:0] user_irq_core;
|
|
|
|
wire [2:0] user_irq_ena;
|
2021-10-25 14:08:13 -05:00
|
|
|
wire [2:0] irq_spi; // From SPI and external pins
|
2021-10-12 15:31:42 -05:00
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
// Exported Wishbone Bus (processor facing)
|
2022-04-25 10:50:55 -05:00
|
|
|
wire mprj_iena_wb;
|
2021-10-12 15:31:42 -05:00
|
|
|
wire mprj_cyc_o_core;
|
|
|
|
wire mprj_stb_o_core;
|
|
|
|
wire mprj_we_o_core;
|
|
|
|
wire [3:0] mprj_sel_o_core;
|
|
|
|
wire [31:0] mprj_adr_o_core;
|
|
|
|
wire [31:0] mprj_dat_o_core;
|
2021-10-27 18:36:43 -05:00
|
|
|
wire mprj_ack_i_core;
|
2021-10-12 15:31:42 -05:00
|
|
|
wire [31:0] mprj_dat_i_core;
|
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
wire [31:0] hk_dat_i;
|
|
|
|
wire hk_ack_i;
|
|
|
|
wire hk_stb_o;
|
2021-11-29 13:27:02 -06:00
|
|
|
wire hk_cyc_o;
|
2021-10-25 14:08:13 -05:00
|
|
|
|
|
|
|
// Exported Wishbone Bus (user area facing)
|
|
|
|
wire mprj_cyc_o_user;
|
|
|
|
wire mprj_stb_o_user;
|
|
|
|
wire mprj_we_o_user;
|
|
|
|
wire [3:0] mprj_sel_o_user;
|
|
|
|
wire [31:0] mprj_adr_o_user;
|
|
|
|
wire [31:0] mprj_dat_o_user;
|
2021-10-27 18:36:43 -05:00
|
|
|
wire mprj_ack_i_user;
|
|
|
|
wire [31:0] mprj_dat_i_user;
|
2021-10-25 14:08:13 -05:00
|
|
|
|
2021-10-12 15:31:42 -05:00
|
|
|
// Mask revision
|
|
|
|
wire [31:0] mask_rev;
|
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
wire mprj_clock;
|
|
|
|
wire mprj_clock2;
|
|
|
|
wire mprj_reset;
|
|
|
|
|
|
|
|
// Power monitoring
|
|
|
|
wire mprj_vcc_pwrgood;
|
|
|
|
wire mprj2_vcc_pwrgood;
|
|
|
|
wire mprj_vdd_pwrgood;
|
|
|
|
wire mprj2_vdd_pwrgood;
|
|
|
|
|
|
|
|
// SRAM read-noly access from housekeeping
|
|
|
|
wire hkspi_sram_clk;
|
|
|
|
wire hkspi_sram_csb;
|
|
|
|
wire [7:0] hkspi_sram_addr;
|
|
|
|
wire [31:0] hkspi_sram_data;
|
|
|
|
|
|
|
|
// Management processor (wrapper). Any management core
|
|
|
|
// implementation must match this pinout.
|
|
|
|
|
|
|
|
mgmt_core_wrapper soc (
|
2021-10-12 15:31:42 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
2021-10-25 14:08:13 -05:00
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
2021-10-12 15:31:42 -05:00
|
|
|
`endif
|
2021-10-25 14:08:13 -05:00
|
|
|
|
|
|
|
// Clocks and reset
|
|
|
|
.core_clk(caravel_clk),
|
|
|
|
.core_rstn(caravel_rstn),
|
|
|
|
|
|
|
|
// GPIO (1 pin)
|
|
|
|
.gpio_out_pad(gpio_out_core),
|
|
|
|
.gpio_in_pad(gpio_in_core),
|
|
|
|
.gpio_mode0_pad(gpio_mode0_core),
|
|
|
|
.gpio_mode1_pad(gpio_mode1_core),
|
|
|
|
.gpio_outenb_pad(gpio_outenb_core),
|
|
|
|
.gpio_inenb_pad(gpio_inenb_core),
|
|
|
|
|
|
|
|
// Primary SPI flash controller
|
|
|
|
.flash_csb(flash_csb_core),
|
|
|
|
.flash_clk(flash_clk_core),
|
|
|
|
.flash_io0_oeb(flash_io0_oeb_core),
|
|
|
|
.flash_io0_di(flash_io0_di_core),
|
|
|
|
.flash_io0_do(flash_io0_do_core),
|
|
|
|
.flash_io1_oeb(flash_io1_oeb_core),
|
|
|
|
.flash_io1_di(flash_io1_di_core),
|
|
|
|
.flash_io1_do(flash_io1_do_core),
|
|
|
|
.flash_io2_oeb(flash_io2_oeb_core),
|
|
|
|
.flash_io2_di(flash_io2_di_core),
|
|
|
|
.flash_io2_do(flash_io2_do_core),
|
|
|
|
.flash_io3_oeb(flash_io3_oeb_core),
|
|
|
|
.flash_io3_di(flash_io3_di_core),
|
|
|
|
.flash_io3_do(flash_io3_do_core),
|
|
|
|
|
|
|
|
// Exported Wishbone Bus
|
2022-04-25 10:50:55 -05:00
|
|
|
.mprj_wb_iena(mprj_iena_wb),
|
2021-10-25 14:08:13 -05:00
|
|
|
.mprj_cyc_o(mprj_cyc_o_core),
|
|
|
|
.mprj_stb_o(mprj_stb_o_core),
|
|
|
|
.mprj_we_o(mprj_we_o_core),
|
|
|
|
.mprj_sel_o(mprj_sel_o_core),
|
|
|
|
.mprj_adr_o(mprj_adr_o_core),
|
|
|
|
.mprj_dat_o(mprj_dat_o_core),
|
|
|
|
.mprj_ack_i(mprj_ack_i_core),
|
|
|
|
.mprj_dat_i(mprj_dat_i_core),
|
|
|
|
|
|
|
|
.hk_stb_o(hk_stb_o),
|
2021-11-29 13:27:02 -06:00
|
|
|
.hk_cyc_o(hk_cyc_o),
|
2021-10-25 14:08:13 -05:00
|
|
|
.hk_dat_i(hk_dat_i),
|
|
|
|
.hk_ack_i(hk_ack_i),
|
|
|
|
|
|
|
|
// IRQ
|
|
|
|
.irq({irq_spi, user_irq}),
|
2022-04-19 21:05:27 -05:00
|
|
|
.user_irq_ena(user_irq_ena),
|
2021-10-25 14:08:13 -05:00
|
|
|
|
|
|
|
// Module status (these may or may not be implemented)
|
|
|
|
.qspi_enabled(qspi_enabled),
|
|
|
|
.uart_enabled(uart_enabled),
|
|
|
|
.spi_enabled(spi_enabled),
|
|
|
|
.debug_mode(debug_mode),
|
|
|
|
|
|
|
|
// Module I/O (these may or may not be implemented)
|
|
|
|
// UART
|
|
|
|
.ser_tx(ser_tx),
|
|
|
|
.ser_rx(ser_rx),
|
|
|
|
// SPI master
|
|
|
|
.spi_sdi(spi_sdi),
|
|
|
|
.spi_csb(spi_csb),
|
|
|
|
.spi_sck(spi_sck),
|
|
|
|
.spi_sdo(spi_sdo),
|
|
|
|
.spi_sdoenb(spi_sdoenb),
|
|
|
|
// Debug
|
|
|
|
.debug_in(debug_in),
|
|
|
|
.debug_out(debug_out),
|
|
|
|
.debug_oeb(debug_oeb),
|
|
|
|
// Logic analyzer
|
|
|
|
.la_input(la_data_in_mprj),
|
|
|
|
.la_output(la_data_out_mprj),
|
|
|
|
.la_oenb(la_oenb_mprj),
|
|
|
|
.la_iena(la_iena_mprj),
|
|
|
|
|
|
|
|
// SRAM Read-only access from housekeeping
|
|
|
|
.sram_ro_clk(hkspi_sram_clk),
|
|
|
|
.sram_ro_csb(hkspi_sram_csb),
|
|
|
|
.sram_ro_addr(hkspi_sram_addr),
|
|
|
|
.sram_ro_data(hkspi_sram_data),
|
|
|
|
|
|
|
|
// Trap status
|
|
|
|
.trap(trap)
|
|
|
|
);
|
|
|
|
|
|
|
|
/* Clock and reset to user space are passed through a tristate */
|
|
|
|
/* buffer like the above, but since they are intended to be */
|
|
|
|
/* always active, connect the enable to the logic-1 output from */
|
|
|
|
/* the vccd1 domain. */
|
|
|
|
|
|
|
|
mgmt_protect mgmt_buffers (
|
2021-10-12 15:31:42 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
2021-10-25 14:08:13 -05:00
|
|
|
.vccd(vccd_core),
|
|
|
|
.vssd(vssd_core),
|
|
|
|
.vccd1(vccd1_core),
|
|
|
|
.vssd1(vssd1_core),
|
|
|
|
.vccd2(vccd2_core),
|
|
|
|
.vssd2(vssd2_core),
|
|
|
|
.vdda1(vdda1_core),
|
|
|
|
.vssa1(vssa1_core),
|
|
|
|
.vdda2(vdda2_core),
|
|
|
|
.vssa2(vssa2_core),
|
|
|
|
`endif
|
|
|
|
.caravel_clk(caravel_clk),
|
|
|
|
.caravel_clk2(caravel_clk2),
|
|
|
|
.caravel_rstn(caravel_rstn),
|
2021-10-27 18:36:43 -05:00
|
|
|
.mprj_iena_wb(mprj_iena_wb),
|
2021-10-25 14:08:13 -05:00
|
|
|
.mprj_cyc_o_core(mprj_cyc_o_core),
|
|
|
|
.mprj_stb_o_core(mprj_stb_o_core),
|
|
|
|
.mprj_we_o_core(mprj_we_o_core),
|
|
|
|
.mprj_sel_o_core(mprj_sel_o_core),
|
|
|
|
.mprj_adr_o_core(mprj_adr_o_core),
|
|
|
|
.mprj_dat_o_core(mprj_dat_o_core),
|
2021-10-27 18:36:43 -05:00
|
|
|
.mprj_dat_i_core(mprj_dat_i_core),
|
|
|
|
.mprj_ack_i_core(mprj_ack_i_core),
|
2021-10-25 14:08:13 -05:00
|
|
|
.user_irq_core(user_irq_core),
|
|
|
|
.la_data_out_core(la_data_out_user),
|
|
|
|
.la_data_out_mprj(la_data_out_mprj),
|
|
|
|
.la_data_in_core(la_data_in_user),
|
|
|
|
.la_data_in_mprj(la_data_in_mprj),
|
|
|
|
.la_oenb_mprj(la_oenb_mprj),
|
|
|
|
.la_oenb_core(la_oenb_user),
|
|
|
|
.la_iena_mprj(la_iena_mprj),
|
|
|
|
.user_irq_ena(user_irq_ena),
|
|
|
|
|
|
|
|
.user_clock(mprj_clock),
|
|
|
|
.user_clock2(mprj_clock2),
|
|
|
|
.user_reset(mprj_reset),
|
|
|
|
.mprj_cyc_o_user(mprj_cyc_o_user),
|
|
|
|
.mprj_stb_o_user(mprj_stb_o_user),
|
|
|
|
.mprj_we_o_user(mprj_we_o_user),
|
|
|
|
.mprj_sel_o_user(mprj_sel_o_user),
|
|
|
|
.mprj_adr_o_user(mprj_adr_o_user),
|
|
|
|
.mprj_dat_o_user(mprj_dat_o_user),
|
2021-10-27 18:36:43 -05:00
|
|
|
.mprj_dat_i_user(mprj_dat_i_user),
|
|
|
|
.mprj_ack_i_user(mprj_ack_i_user),
|
2021-10-25 14:08:13 -05:00
|
|
|
.user_irq(user_irq),
|
|
|
|
.user1_vcc_powergood(mprj_vcc_pwrgood),
|
|
|
|
.user2_vcc_powergood(mprj2_vcc_pwrgood),
|
|
|
|
.user1_vdd_powergood(mprj_vdd_pwrgood),
|
|
|
|
.user2_vdd_powergood(mprj2_vdd_pwrgood)
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
/*--------------------------------------------------*/
|
|
|
|
/* Wrapper module around the user project */
|
|
|
|
/*--------------------------------------------------*/
|
|
|
|
|
|
|
|
assign user_io_in_3v3 = mprj_io_in_3v3;
|
2021-10-12 15:31:42 -05:00
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
user_analog_project_wrapper mprj (
|
2021-10-12 15:31:42 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
2021-10-25 14:08:13 -05:00
|
|
|
.vdda1(vdda1_core), // User area 1 3.3V power
|
|
|
|
.vdda2(vdda2_core), // User area 2 3.3V power
|
|
|
|
.vssa1(vssa1_core), // User area 1 analog ground
|
|
|
|
.vssa2(vssa2_core), // User area 2 analog ground
|
|
|
|
.vccd1(vccd1_core), // User area 1 1.8V power
|
|
|
|
.vccd2(vccd2_core), // User area 2 1.8V power
|
|
|
|
.vssd1(vssd1_core), // User area 1 digital ground
|
|
|
|
.vssd2(vssd2_core), // User area 2 digital ground
|
|
|
|
`endif
|
|
|
|
|
|
|
|
.wb_clk_i(mprj_clock),
|
|
|
|
.wb_rst_i(mprj_reset),
|
|
|
|
|
|
|
|
// MGMT SoC Wishbone Slave
|
|
|
|
.wbs_cyc_i(mprj_cyc_o_user),
|
|
|
|
.wbs_stb_i(mprj_stb_o_user),
|
|
|
|
.wbs_we_i(mprj_we_o_user),
|
|
|
|
.wbs_sel_i(mprj_sel_o_user),
|
|
|
|
.wbs_adr_i(mprj_adr_o_user),
|
|
|
|
.wbs_dat_i(mprj_dat_o_user),
|
2021-10-27 18:36:43 -05:00
|
|
|
.wbs_ack_o(mprj_ack_i_user),
|
|
|
|
.wbs_dat_o(mprj_dat_i_user),
|
2021-10-25 14:08:13 -05:00
|
|
|
|
|
|
|
// GPIO pad 3-pin interface (plus analog)
|
|
|
|
.io_in (user_io_in),
|
|
|
|
.io_in_3v3 (user_io_in_3v3),
|
|
|
|
.io_out(user_io_out),
|
|
|
|
.io_oeb(user_io_oeb),
|
|
|
|
.io_analog(user_analog),
|
|
|
|
.gpio_analog(user_gpio_analog),
|
|
|
|
.gpio_noesd(user_gpio_noesd),
|
|
|
|
|
|
|
|
// Logic Analyzer
|
|
|
|
.la_data_in(la_data_in_user),
|
|
|
|
.la_data_out(la_data_out_user),
|
|
|
|
.la_oenb(la_oenb_user),
|
|
|
|
|
|
|
|
// User-accessible power supply clamps
|
|
|
|
.io_clamp_high(user_clamp_high),
|
|
|
|
.io_clamp_low(user_clamp_low),
|
|
|
|
|
|
|
|
// Independent clock
|
|
|
|
.user_clock2(mprj_clock2),
|
|
|
|
|
|
|
|
// IRQ
|
|
|
|
.user_irq(user_irq_core)
|
|
|
|
);
|
|
|
|
|
|
|
|
/*--------------------------------------*/
|
|
|
|
/* End user project instantiation */
|
|
|
|
/*--------------------------------------*/
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1:0] gpio_serial_link_1_shifted;
|
|
|
|
wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:0] gpio_serial_link_2_shifted;
|
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1
|
|
|
|
-`ANALOG_PADS_1-2:0],
|
2021-10-12 15:31:42 -05:00
|
|
|
mprj_io_loader_data_1};
|
|
|
|
// Note that serial_link_2 is backwards compared to serial_link_1, so it
|
|
|
|
// shifts in the other direction.
|
|
|
|
assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2,
|
2021-10-25 14:08:13 -05:00
|
|
|
gpio_serial_link_2[`MPRJ_IO_PADS_2
|
|
|
|
-`ANALOG_PADS_2-1:1]};
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
// Propagating clock and reset to mitigate timing and fanout issues
|
|
|
|
wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
|
|
|
|
wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
|
|
|
|
wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
|
|
|
|
wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
|
2021-11-03 22:18:36 -05:00
|
|
|
wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1;
|
|
|
|
wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2;
|
2021-10-12 15:31:42 -05:00
|
|
|
wire [`MPRJ_IO_PADS_1-6:0] gpio_clock_1_shifted;
|
|
|
|
wire [`MPRJ_IO_PADS_2-7:0] gpio_clock_2_shifted;
|
|
|
|
wire [`MPRJ_IO_PADS_1-6:0] gpio_resetn_1_shifted;
|
|
|
|
wire [`MPRJ_IO_PADS_2-7:0] gpio_resetn_2_shifted;
|
2021-11-03 22:18:36 -05:00
|
|
|
wire [`MPRJ_IO_PADS_1-6:0] gpio_load_1_shifted;
|
|
|
|
wire [`MPRJ_IO_PADS_2-7:0] gpio_load_2_shifted;
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-2:0],
|
|
|
|
mprj_io_loader_clock};
|
|
|
|
assign gpio_clock_2_shifted = {mprj_io_loader_clock,
|
|
|
|
gpio_clock_2[`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:1]};
|
|
|
|
assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-2:0],
|
|
|
|
mprj_io_loader_resetn};
|
|
|
|
assign gpio_resetn_2_shifted = {mprj_io_loader_resetn,
|
|
|
|
gpio_resetn_2[`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:1]};
|
2021-11-03 22:18:36 -05:00
|
|
|
assign gpio_load_1_shifted = {gpio_load_1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-2:0],
|
|
|
|
mprj_io_loader_strobe};
|
|
|
|
assign gpio_load_2_shifted = {mprj_io_loader_strobe,
|
|
|
|
gpio_load_2[`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:1]};
|
2021-10-12 15:31:42 -05:00
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
wire [2:0] spi_pll_sel;
|
|
|
|
wire [2:0] spi_pll90_sel;
|
|
|
|
wire [4:0] spi_pll_div;
|
|
|
|
wire [25:0] spi_pll_trim;
|
|
|
|
|
|
|
|
// Clocking control
|
|
|
|
|
2022-04-07 09:44:57 -05:00
|
|
|
caravel_clocking clock_ctrl (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
2021-11-22 08:46:21 -06:00
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
2021-10-25 14:08:13 -05:00
|
|
|
`endif
|
|
|
|
.ext_clk_sel(ext_clk_sel),
|
2021-11-17 08:06:42 -06:00
|
|
|
.ext_clk(clock_core),
|
2021-10-25 14:08:13 -05:00
|
|
|
.pll_clk(pll_clk),
|
|
|
|
.pll_clk90(pll_clk90),
|
2021-11-22 12:25:35 -06:00
|
|
|
.resetb(rstb_l),
|
2021-10-25 14:08:13 -05:00
|
|
|
.sel(spi_pll_sel),
|
|
|
|
.sel2(spi_pll90_sel),
|
|
|
|
.ext_reset(ext_reset), // From housekeeping SPI
|
|
|
|
.core_clk(caravel_clk),
|
|
|
|
.user_clk(caravel_clk2),
|
|
|
|
.resetb_sync(caravel_rstn)
|
|
|
|
);
|
|
|
|
|
|
|
|
// DCO/Digital Locked Loop
|
|
|
|
|
|
|
|
digital_pll pll (
|
|
|
|
`ifdef USE_POWER_PINS
|
2021-11-17 08:06:42 -06:00
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
2021-10-25 14:08:13 -05:00
|
|
|
`endif
|
2021-11-22 12:25:35 -06:00
|
|
|
.resetb(rstb_l),
|
2021-10-25 14:08:13 -05:00
|
|
|
.enable(spi_pll_ena),
|
2021-11-22 12:25:35 -06:00
|
|
|
.osc(clock_core),
|
2021-10-25 14:08:13 -05:00
|
|
|
.clockp({pll_clk, pll_clk90}),
|
|
|
|
.div(spi_pll_div),
|
|
|
|
.dco(spi_pll_dco_ena),
|
|
|
|
.ext_trim(spi_pll_trim)
|
|
|
|
);
|
|
|
|
|
|
|
|
// Housekeeping interface
|
|
|
|
|
|
|
|
housekeeping housekeeping (
|
|
|
|
`ifdef USE_POWER_PINS
|
2021-11-22 08:46:21 -06:00
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
2021-10-25 14:08:13 -05:00
|
|
|
`endif
|
|
|
|
|
2021-11-03 10:30:39 -05:00
|
|
|
.wb_clk_i(caravel_clk),
|
2021-11-22 08:46:21 -06:00
|
|
|
.wb_rstn_i(caravel_rstn),
|
2021-10-25 14:08:13 -05:00
|
|
|
|
|
|
|
.wb_adr_i(mprj_adr_o_core),
|
|
|
|
.wb_dat_i(mprj_dat_o_core),
|
|
|
|
.wb_sel_i(mprj_sel_o_core),
|
|
|
|
.wb_we_i(mprj_we_o_core),
|
2021-11-29 13:27:02 -06:00
|
|
|
.wb_cyc_i(hk_cyc_o),
|
2021-10-25 14:08:13 -05:00
|
|
|
.wb_stb_i(hk_stb_o),
|
|
|
|
.wb_ack_o(hk_ack_i),
|
|
|
|
.wb_dat_o(hk_dat_i),
|
|
|
|
|
|
|
|
.porb(porb_l),
|
|
|
|
|
|
|
|
.pll_ena(spi_pll_ena),
|
|
|
|
.pll_dco_ena(spi_pll_dco_ena),
|
|
|
|
.pll_div(spi_pll_div),
|
|
|
|
.pll_sel(spi_pll_sel),
|
|
|
|
.pll90_sel(spi_pll90_sel),
|
|
|
|
.pll_trim(spi_pll_trim),
|
|
|
|
.pll_bypass(ext_clk_sel),
|
|
|
|
|
|
|
|
.qspi_enabled(qspi_enabled),
|
|
|
|
.uart_enabled(uart_enabled),
|
|
|
|
.spi_enabled(spi_enabled),
|
|
|
|
.debug_mode(debug_mode),
|
|
|
|
|
|
|
|
.ser_tx(ser_tx),
|
|
|
|
.ser_rx(ser_rx),
|
|
|
|
|
|
|
|
.spi_sdi(spi_sdi),
|
|
|
|
.spi_csb(spi_csb),
|
|
|
|
.spi_sck(spi_sck),
|
|
|
|
.spi_sdo(spi_sdo),
|
|
|
|
.spi_sdoenb(spi_sdoenb),
|
|
|
|
|
|
|
|
.debug_in(debug_in),
|
|
|
|
.debug_out(debug_out),
|
|
|
|
.debug_oeb(debug_oeb),
|
|
|
|
|
|
|
|
.irq(irq_spi),
|
|
|
|
.reset(ext_reset),
|
|
|
|
|
|
|
|
.serial_clock(mprj_io_loader_clock),
|
2021-11-03 22:18:36 -05:00
|
|
|
.serial_load(mprj_io_loader_strobe),
|
2021-10-25 14:08:13 -05:00
|
|
|
.serial_resetn(mprj_io_loader_resetn),
|
|
|
|
.serial_data_1(mprj_io_loader_data_1),
|
|
|
|
.serial_data_2(mprj_io_loader_data_2),
|
|
|
|
|
|
|
|
.mgmt_gpio_in(mgmt_io_in),
|
|
|
|
.mgmt_gpio_out({mgmt_io_out[4:2], mgmt_io_in[`MPRJ_IO_PADS-4:2],
|
|
|
|
mgmt_io_out[1:0]}),
|
|
|
|
.mgmt_gpio_oeb({mgmt_io_oeb[4:2], mgmt_io_nc[`MPRJ_IO_PADS-6:0],
|
|
|
|
mgmt_io_oeb[1:0]}),
|
|
|
|
|
2021-11-21 21:58:39 -06:00
|
|
|
.pwr_ctrl_out(pwr_ctrl_nc), /* Not used in this version */
|
2021-10-25 14:08:13 -05:00
|
|
|
|
|
|
|
.trap(trap),
|
|
|
|
|
2021-12-06 18:38:24 -06:00
|
|
|
.user_clock(caravel_clk2),
|
2021-10-25 14:08:13 -05:00
|
|
|
|
|
|
|
.mask_rev_in(mask_rev),
|
|
|
|
|
|
|
|
.spimemio_flash_csb(flash_csb_core),
|
|
|
|
.spimemio_flash_clk(flash_clk_core),
|
|
|
|
.spimemio_flash_io0_oeb(flash_io0_oeb_core),
|
|
|
|
.spimemio_flash_io1_oeb(flash_io1_oeb_core),
|
|
|
|
.spimemio_flash_io2_oeb(flash_io2_oeb_core),
|
|
|
|
.spimemio_flash_io3_oeb(flash_io3_oeb_core),
|
|
|
|
.spimemio_flash_io0_do(flash_io0_do_core),
|
|
|
|
.spimemio_flash_io1_do(flash_io1_do_core),
|
|
|
|
.spimemio_flash_io2_do(flash_io2_do_core),
|
|
|
|
.spimemio_flash_io3_do(flash_io3_do_core),
|
|
|
|
.spimemio_flash_io0_di(flash_io0_di_core),
|
|
|
|
.spimemio_flash_io1_di(flash_io1_di_core),
|
|
|
|
.spimemio_flash_io2_di(flash_io2_di_core),
|
|
|
|
.spimemio_flash_io3_di(flash_io3_di_core),
|
|
|
|
|
|
|
|
.pad_flash_csb(flash_csb_frame),
|
|
|
|
.pad_flash_csb_oeb(flash_csb_oeb),
|
|
|
|
.pad_flash_clk(flash_clk_frame),
|
|
|
|
.pad_flash_clk_oeb(flash_clk_oeb),
|
|
|
|
.pad_flash_io0_oeb(flash_io0_oeb),
|
|
|
|
.pad_flash_io1_oeb(flash_io1_oeb),
|
|
|
|
.pad_flash_io0_ieb(flash_io0_ieb),
|
|
|
|
.pad_flash_io1_ieb(flash_io1_ieb),
|
|
|
|
.pad_flash_io0_do(flash_io0_do),
|
|
|
|
.pad_flash_io1_do(flash_io1_do),
|
|
|
|
.pad_flash_io0_di(flash_io0_di),
|
|
|
|
.pad_flash_io1_di(flash_io1_di),
|
|
|
|
|
|
|
|
.sram_ro_clk(hkspi_sram_clk),
|
|
|
|
.sram_ro_csb(hkspi_sram_csb),
|
|
|
|
.sram_ro_addr(hkspi_sram_addr),
|
|
|
|
.sram_ro_data(hkspi_sram_data),
|
|
|
|
|
|
|
|
.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
|
|
|
|
.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
|
|
|
|
.usr1_vdd_pwrgood(mprj_vdd_pwrgood),
|
|
|
|
.usr2_vdd_pwrgood(mprj2_vdd_pwrgood)
|
|
|
|
);
|
|
|
|
|
|
|
|
/* GPIO defaults (via programmed) */
|
|
|
|
wire [(`MPRJ_IO_PADS - `ANALOG_PADS)*13-1:0] gpio_defaults;
|
|
|
|
|
|
|
|
/* Fixed defaults for the first 5 GPIO pins */
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(13'h1803)
|
2022-09-27 19:58:57 -05:00
|
|
|
) gpio_defaults_block_0 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
2022-09-27 19:58:57 -05:00
|
|
|
.gpio_defaults(gpio_defaults[12:0])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(13'h1803)
|
|
|
|
) gpio_defaults_block_1 (
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[25:13])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(13'h0403)
|
|
|
|
) gpio_defaults_block_2 (
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[38:26])
|
|
|
|
);
|
|
|
|
|
|
|
|
// CSB is configured to be a weak pull-up
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(13'h0c01)
|
|
|
|
) gpio_defaults_block_3 (
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[51:39])
|
2021-10-25 14:08:13 -05:00
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(13'h0403)
|
2022-09-27 19:58:57 -05:00
|
|
|
) gpio_defaults_block_4 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
2022-09-27 19:58:57 -05:00
|
|
|
.gpio_defaults(gpio_defaults[64:52])
|
2021-10-25 14:08:13 -05:00
|
|
|
);
|
|
|
|
|
|
|
|
/* Via-programmable defaults for the rest of the GPIO pins */
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_5_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_5 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[77:65])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_6_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_6 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[90:78])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_7_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_7 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[103:91])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_8_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_8 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[116:104])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_9_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_9 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[129:117])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_10_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_10 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[142:130])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_11_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_11 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[155:143])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_12_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_12 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[168:156])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_13_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_13 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[181:169])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_14 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[194:182])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_26_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_26 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[207:195])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_27_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_27 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[220:208])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_28_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_28 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[233:221])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_29_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_29 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[246:234])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_30_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_30 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[259:247])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_31_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_31 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[272:260])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_32_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_32 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[285:273])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_33_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_33 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[298:286])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_34_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_34 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[311:299])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_35_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_35 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[324:312])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_36_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_36 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[337:325])
|
|
|
|
);
|
|
|
|
|
|
|
|
gpio_defaults_block #(
|
|
|
|
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_37_INIT)
|
2021-11-29 18:57:33 -06:00
|
|
|
) gpio_defaults_block_37 (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.gpio_defaults(gpio_defaults[350:338])
|
|
|
|
);
|
|
|
|
|
2021-10-12 15:31:42 -05:00
|
|
|
// Each control block sits next to an I/O pad in the user area.
|
|
|
|
// It gets input through a serial chain from the previous control
|
|
|
|
// block and passes it to the next control block. Due to the nature
|
|
|
|
// of the shift register, bits are presented in reverse, as the first
|
|
|
|
// bit in ends up as the last bit of the last I/O pad control block.
|
|
|
|
|
|
|
|
// There are two types of block; the first two and the last two
|
|
|
|
// are configured to be full bidirectional under control of the
|
|
|
|
// management Soc (JTAG and SDO for the first two; flash_io2 and
|
|
|
|
// flash_io3 for the last two). The rest are configured to be default
|
|
|
|
// (input). Note that the first two and last two are the ones closest
|
|
|
|
// to the management SoC on either side, which minimizes the wire length
|
|
|
|
// of the extra signals those pads need.
|
|
|
|
|
|
|
|
/* First two GPIOs (JTAG and SDO) */
|
2021-10-25 14:08:13 -05:00
|
|
|
gpio_control_block gpio_control_bidir_1 [1:0] (
|
2021-10-12 15:31:42 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
2021-10-25 14:08:13 -05:00
|
|
|
.vccd(vccd_core),
|
|
|
|
.vssd(vssd_core),
|
|
|
|
.vccd1(vccd1_core),
|
|
|
|
.vssd1(vssd1_core),
|
|
|
|
`endif
|
|
|
|
|
|
|
|
.gpio_defaults(gpio_defaults[25:0]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
// Management Soc-facing signals
|
|
|
|
|
|
|
|
.resetn(gpio_resetn_1_shifted[1:0]),
|
|
|
|
.serial_clock(gpio_clock_1_shifted[1:0]),
|
2021-11-03 22:18:36 -05:00
|
|
|
.serial_load(gpio_load_1_shifted[1:0]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
.resetn_out(gpio_resetn_1[1:0]),
|
|
|
|
.serial_clock_out(gpio_clock_1[1:0]),
|
2021-11-03 22:18:36 -05:00
|
|
|
.serial_load_out(gpio_load_1[1:0]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
.mgmt_gpio_in(mgmt_io_in[1:0]),
|
2022-04-25 10:50:55 -05:00
|
|
|
.mgmt_gpio_out(mgmt_io_out[1:0]),
|
|
|
|
.mgmt_gpio_oeb(mgmt_io_oeb[1:0]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
.one(),
|
|
|
|
.zero(),
|
|
|
|
|
|
|
|
// Serial data chain for pad configuration
|
|
|
|
.serial_data_in(gpio_serial_link_1_shifted[1:0]),
|
|
|
|
.serial_data_out(gpio_serial_link_1[1:0]),
|
|
|
|
|
|
|
|
// User-facing signals
|
|
|
|
.user_gpio_out(user_io_out[1:0]),
|
|
|
|
.user_gpio_oeb(user_io_oeb[1:0]),
|
|
|
|
.user_gpio_in(user_io_in[1:0]),
|
|
|
|
|
|
|
|
// Pad-facing signals (Pad GPIOv2)
|
|
|
|
.pad_gpio_inenb(mprj_io_inp_dis[1:0]),
|
|
|
|
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
|
|
|
|
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
|
|
|
|
.pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
|
|
|
|
.pad_gpio_holdover(mprj_io_holdover[1:0]),
|
|
|
|
.pad_gpio_ana_en(mprj_io_analog_en[1:0]),
|
|
|
|
.pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
|
|
|
|
.pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
|
|
|
|
.pad_gpio_dm(mprj_io_dm[5:0]),
|
|
|
|
.pad_gpio_outenb(mprj_io_oeb[1:0]),
|
|
|
|
.pad_gpio_out(mprj_io_out[1:0]),
|
|
|
|
.pad_gpio_in(mprj_io_in[1:0])
|
|
|
|
);
|
|
|
|
|
|
|
|
/* Section 1 GPIOs (GPIO 0 to 18) */
|
|
|
|
wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:0] one_loop1;
|
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
/* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
|
2021-10-12 15:31:42 -05:00
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
gpio_control_block gpio_control_in_1a [5:0] (
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.vccd(vccd_core),
|
|
|
|
.vssd(vssd_core),
|
|
|
|
.vccd1(vccd1_core),
|
|
|
|
.vssd1(vssd1_core),
|
|
|
|
`endif
|
2021-10-12 15:31:42 -05:00
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
.gpio_defaults(gpio_defaults[103:26]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
// Management Soc-facing signals
|
|
|
|
|
|
|
|
.resetn(gpio_resetn_1_shifted[7:2]),
|
|
|
|
.serial_clock(gpio_clock_1_shifted[7:2]),
|
2021-11-03 22:18:36 -05:00
|
|
|
.serial_load(gpio_load_1_shifted[7:2]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
.resetn_out(gpio_resetn_1[7:2]),
|
|
|
|
.serial_clock_out(gpio_clock_1[7:2]),
|
2021-11-03 22:18:36 -05:00
|
|
|
.serial_load_out(gpio_load_1[7:2]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
.mgmt_gpio_in(mgmt_io_in[7:2]),
|
|
|
|
.mgmt_gpio_out(mgmt_io_in[7:2]),
|
|
|
|
.mgmt_gpio_oeb(one_loop1[5:0]),
|
|
|
|
|
|
|
|
.one(one_loop1[5:0]),
|
|
|
|
.zero(),
|
|
|
|
|
|
|
|
// Serial data chain for pad configuration
|
|
|
|
.serial_data_in(gpio_serial_link_1_shifted[7:2]),
|
|
|
|
.serial_data_out(gpio_serial_link_1[7:2]),
|
|
|
|
|
|
|
|
// User-facing signals
|
|
|
|
.user_gpio_out(user_io_out[7:2]),
|
|
|
|
.user_gpio_oeb(user_io_oeb[7:2]),
|
|
|
|
.user_gpio_in(user_io_in[7:2]),
|
|
|
|
|
|
|
|
// Pad-facing signals (Pad GPIOv2)
|
|
|
|
.pad_gpio_inenb(mprj_io_inp_dis[7:2]),
|
|
|
|
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[7:2]),
|
|
|
|
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[7:2]),
|
|
|
|
.pad_gpio_slow_sel(mprj_io_slow_sel[7:2]),
|
|
|
|
.pad_gpio_holdover(mprj_io_holdover[7:2]),
|
|
|
|
.pad_gpio_ana_en(mprj_io_analog_en[7:2]),
|
|
|
|
.pad_gpio_ana_sel(mprj_io_analog_sel[7:2]),
|
|
|
|
.pad_gpio_ana_pol(mprj_io_analog_pol[7:2]),
|
|
|
|
.pad_gpio_dm(mprj_io_dm[23:6]),
|
|
|
|
.pad_gpio_outenb(mprj_io_oeb[7:2]),
|
|
|
|
.pad_gpio_out(mprj_io_out[7:2]),
|
|
|
|
.pad_gpio_in(mprj_io_in[7:2])
|
|
|
|
);
|
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
/* Section 1 GPIOs (GPIO 8 to 18) */
|
|
|
|
gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-9:0] (
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.vccd(vccd_core),
|
|
|
|
.vssd(vssd_core),
|
|
|
|
.vccd1(vccd1_core),
|
|
|
|
.vssd1(vssd1_core),
|
|
|
|
`endif
|
|
|
|
|
|
|
|
.gpio_defaults(gpio_defaults[((`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*13-1):104]),
|
|
|
|
|
|
|
|
// Management Soc-facing signals
|
|
|
|
|
|
|
|
.resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
2021-11-03 22:18:36 -05:00
|
|
|
.serial_load(gpio_load_1_shifted[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
2021-10-25 14:08:13 -05:00
|
|
|
|
|
|
|
.resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
2021-11-03 22:18:36 -05:00
|
|
|
.serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
2021-10-25 14:08:13 -05:00
|
|
|
|
|
|
|
.mgmt_gpio_in(mgmt_io_in[`DIG1_TOP:8]),
|
|
|
|
.mgmt_gpio_out(mgmt_io_in[`DIG1_TOP:8]),
|
|
|
|
.mgmt_gpio_oeb(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]),
|
|
|
|
|
|
|
|
.one(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]),
|
|
|
|
.zero(),
|
|
|
|
|
|
|
|
// Serial data chain for pad configuration
|
|
|
|
.serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
|
|
|
|
// User-facing signals
|
|
|
|
.user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
|
|
|
|
// Pad-facing signals (Pad GPIOv2)
|
|
|
|
.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*3-1:24]),
|
|
|
|
.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
|
|
|
|
.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8])
|
|
|
|
);
|
|
|
|
|
|
|
|
/* Last three GPIOs (spi_sdo, flash_io2 and flash_io3) */
|
|
|
|
|
|
|
|
gpio_control_block gpio_control_bidir_2 [2:0] (
|
2021-10-12 15:31:42 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
2021-10-25 14:08:13 -05:00
|
|
|
.vccd(vccd_core),
|
|
|
|
.vssd(vssd_core),
|
|
|
|
.vccd1(vccd1_core),
|
|
|
|
.vssd1(vssd1_core),
|
2021-10-12 15:31:42 -05:00
|
|
|
`endif
|
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
.gpio_defaults(gpio_defaults[((`MPRJ_IO_PADS-`ANALOG_PADS)*13-1):((`MPRJ_IO_PADS-`ANALOG_PADS)*13-39)]),
|
|
|
|
|
2021-10-12 15:31:42 -05:00
|
|
|
// Management Soc-facing signals
|
|
|
|
|
2021-11-22 21:35:52 -06:00
|
|
|
.resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
|
|
|
|
.serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
|
|
|
|
.serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
2021-11-22 21:35:52 -06:00
|
|
|
.resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
|
|
|
|
.serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
|
|
|
|
.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
2021-10-25 14:08:13 -05:00
|
|
|
.mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP):(`DIG2_TOP-2)]),
|
|
|
|
.mgmt_gpio_out(mgmt_io_out[4:2]),
|
|
|
|
.mgmt_gpio_oeb(mgmt_io_oeb[4:2]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
.one(),
|
|
|
|
.zero(),
|
|
|
|
|
|
|
|
// Serial data chain for pad configuration
|
2021-10-25 14:08:13 -05:00
|
|
|
.serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
|
|
|
|
.serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
// User-facing signals
|
2021-10-25 14:08:13 -05:00
|
|
|
.user_gpio_out(user_io_out[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.user_gpio_oeb(user_io_oeb[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.user_gpio_in(user_io_in[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
// Pad-facing signals (Pad GPIOv2)
|
2021-10-25 14:08:13 -05:00
|
|
|
.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.pad_gpio_dm(mprj_io_dm[(`MPRJ_DIG_PADS*3-1):(`MPRJ_DIG_PADS*3-9)]),
|
|
|
|
.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.pad_gpio_out(mprj_io_out[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
|
|
|
|
.pad_gpio_in(mprj_io_in[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)])
|
2021-10-12 15:31:42 -05:00
|
|
|
);
|
|
|
|
|
|
|
|
/* Section 2 GPIOs (GPIO 19 to 37) */
|
2021-11-22 08:46:21 -06:00
|
|
|
wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4:0] one_loop2;
|
2021-10-25 14:08:13 -05:00
|
|
|
|
2021-11-22 08:46:21 -06:00
|
|
|
gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4:0] (
|
2021-10-25 14:08:13 -05:00
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.vccd(vccd_core),
|
|
|
|
.vssd(vssd_core),
|
|
|
|
.vccd1(vccd1_core),
|
|
|
|
.vssd1(vssd1_core),
|
|
|
|
`endif
|
|
|
|
|
2021-11-22 08:46:21 -06:00
|
|
|
.gpio_defaults(gpio_defaults[((`MPRJ_IO_PADS-`ANALOG_PADS-3)*13-1):((`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*13)]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
// Management Soc-facing signals
|
|
|
|
|
2021-11-22 21:35:52 -06:00
|
|
|
.resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
|
|
|
|
.serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
|
|
|
|
.serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
2021-11-22 21:35:52 -06:00
|
|
|
.resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
|
|
|
|
.serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
|
|
|
|
.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
2021-11-22 08:46:21 -06:00
|
|
|
.mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]),
|
|
|
|
.mgmt_gpio_out(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]),
|
2021-10-25 14:08:13 -05:00
|
|
|
.mgmt_gpio_oeb(one_loop2),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
.one(one_loop2),
|
|
|
|
.zero(),
|
|
|
|
|
|
|
|
// Serial data chain for pad configuration
|
2021-11-22 08:46:21 -06:00
|
|
|
.serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
|
|
|
|
.serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
// User-facing signals
|
2021-11-22 08:46:21 -06:00
|
|
|
.user_gpio_out(user_io_out[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.user_gpio_oeb(user_io_oeb[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.user_gpio_in(user_io_in[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
2021-10-12 15:31:42 -05:00
|
|
|
|
|
|
|
// Pad-facing signals (Pad GPIOv2)
|
2021-11-22 08:46:21 -06:00
|
|
|
.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.pad_gpio_dm(mprj_io_dm[((`MPRJ_DIG_PADS)*3-10):((`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*3)]),
|
|
|
|
.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.pad_gpio_out(mprj_io_out[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
|
|
|
|
.pad_gpio_in(mprj_io_in[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)])
|
2021-10-12 15:31:42 -05:00
|
|
|
);
|
|
|
|
|
|
|
|
user_id_programming #(
|
|
|
|
.USER_PROJECT_ID(USER_PROJECT_ID)
|
|
|
|
) user_id_value (
|
|
|
|
`ifdef USE_POWER_PINS
|
|
|
|
.VPWR(vccd_core),
|
|
|
|
.VGND(vssd_core),
|
|
|
|
`endif
|
|
|
|
.mask_rev(mask_rev)
|
|
|
|
);
|
|
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// Power-on-reset circuit
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simple_por por (
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`ifdef USE_POWER_PINS
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.vdd3v3(vddio_core),
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.vdd1v8(vccd_core),
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2021-11-22 15:51:35 -06:00
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.vss3v3(vssio_core),
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.vss1v8(vssd_core),
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2021-10-12 15:31:42 -05:00
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`endif
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.porb_h(porb_h),
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.porb_l(porb_l),
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.por_l(por_l)
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);
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// XRES (chip input pin reset) reset level converter
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2021-10-31 20:43:09 -05:00
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xres_buf rstb_level (
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2021-10-12 15:31:42 -05:00
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`ifdef USE_POWER_PINS
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.VPWR(vddio_core),
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.LVPWR(vccd_core),
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2021-10-25 14:08:13 -05:00
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.LVGND(vssd_core),
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2021-10-12 15:31:42 -05:00
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.VGND(vssio_core),
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`endif
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.A(rstb_h),
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.X(rstb_l)
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);
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2021-11-24 08:23:22 -06:00
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// Spare logic for metal mask fixes
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2021-11-24 08:34:52 -06:00
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wire [107:0] spare_xz_nc;
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2021-11-24 08:23:22 -06:00
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wire [15:0] spare_xi_nc;
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wire [3:0] spare_xib_nc;
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wire [7:0] spare_xna_nc;
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wire [7:0] spare_xno_nc;
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wire [7:0] spare_xmx_nc;
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wire [7:0] spare_xfq_nc;
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wire [7:0] spare_xfqn_nc;
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spare_logic_block spare_logic [3:0] (
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`ifdef USE_POWER_PINS
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.vccd(vccd_core),
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.vssd(vssd_core),
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`endif
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2021-11-24 08:34:52 -06:00
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.spare_xz(spare_xz_nc),
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2021-11-24 08:23:22 -06:00
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.spare_xi(spare_xi_nc),
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.spare_xib(spare_xib_nc),
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.spare_xna(spare_xna_nc),
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.spare_xno(spare_xno_nc),
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.spare_xmx(spare_xmx_nc),
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.spare_xfq(spare_xfq_nc),
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.spare_xfqn(spare_xfqn_nc)
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);
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2021-10-12 15:31:42 -05:00
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endmodule
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// `default_nettype wire
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