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__uprj_analog_netlists.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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__uprj_netlists.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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__user_analog_project_wrapper.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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__user_project_wrapper.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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caravan.v
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Made modifications in support of changing the hard-coded default
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2022-09-27 20:58:57 -04:00 |
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caravan_netlists.v
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Added a reference to the new file "gl/mgmt_defines.v" in the
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2021-12-24 11:46:34 -05:00 |
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caravan_openframe.v
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Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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2021-10-31 21:43:09 -04:00 |
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caravel.v
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Made modifications in support of changing the hard-coded default
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2022-09-27 20:58:57 -04:00 |
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caravel_clocking.v
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Changed the synchronized reset to occur on the clock falling edge
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2021-12-02 14:26:59 -05:00 |
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caravel_netlists.v
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Added a reference to the new file "gl/mgmt_defines.v" in the
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2021-12-24 11:46:34 -05:00 |
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caravel_openframe.v
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Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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2021-10-31 21:43:09 -04:00 |
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chip_io.v
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A handful of changes/corrections: (1) Housekeeping signal "user_clock"
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2021-12-06 19:38:24 -05:00 |
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chip_io_alt.v
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Caravan top lvs (#67)
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2022-04-14 15:05:16 -07:00 |
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clock_div.v
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Fixed one bad error in clock_div which had been done without my
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2021-12-06 21:37:51 -05:00 |
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defines.v
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Update storage testbench to work with one 2K block
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2021-11-12 17:14:21 +02:00 |
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digital_pll.v
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fixes for RTL testbenches with mgmt core wrapper
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2021-12-05 10:11:10 -08:00 |
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digital_pll_controller.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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gpio_control_block.v
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Modified the GPIO control block verilog to remove the delay stages
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2022-07-24 16:17:56 -04:00 |
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gpio_defaults_block.v
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Implemented a system for setting the GPIO power-on defaults through
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2021-10-23 17:18:30 -04:00 |
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gpio_logic_high.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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housekeeping.v
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Merge branch 'caravel_redesign' into make_CSB_a_pullup
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2022-10-03 17:39:24 -04:00 |
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housekeeping_spi.v
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Modified the housekeeping SPI to generate a read strobe (or rather
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2021-10-23 22:06:24 -04:00 |
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mgmt_protect.v
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Revised the management protect block to include protections against
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2021-10-27 19:36:43 -04:00 |
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mgmt_protect_hv.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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mprj2_logic_high.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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mprj_io.v
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A handful of changes/corrections: (1) Housekeeping signal "user_clock"
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2021-12-06 19:38:24 -05:00 |
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mprj_logic_high.v
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Revised the management protect block to include protections against
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2021-10-27 19:36:43 -04:00 |
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pads.v
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A handful of changes/corrections: (1) Housekeeping signal "user_clock"
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2021-12-06 19:38:24 -05:00 |
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ring_osc2x13.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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simple_por.v
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Modified simple_por.v RTL to avoid the wire declaration that "cvc"
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2021-12-08 12:16:19 -05:00 |
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spare_logic_block.v
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Revised the spare logic block to make sure that all inputs are
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2021-11-24 09:34:52 -05:00 |
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user_defines.v
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Split the layout of the GPIO defaults block into three versions, for the
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2021-11-06 13:28:26 -04:00 |
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user_id_programming.v
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Implemented a system for setting the GPIO power-on defaults through
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2021-10-23 17:18:30 -04:00 |
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xres_buf.v
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Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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2021-10-31 21:43:09 -04:00 |
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