riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
522 Commits 16 Branches 1 Tag 1.8 GiB
Commit Graph

522 Commits

Author SHA1 Message Date
Ganesh Gore 40c131983a [FPGA1212_v1] Changed gds precision to 1000 2020-12-06 01:41:58 -07:00
Ganesh Gore 6af001df11 Added SynRepoConfig is paths 2020-12-06 01:41:58 -07:00
Ganesh Gore 2bada6124f [Action] Changed Docker workdir 2020-12-06 01:41:46 -07:00
Ganesh Gore cfa2bb96c4 [Action] Removed nojekyll file addition 2020-12-06 01:41:46 -07:00
Ganesh Gore 51cd5d6630 [Action] Added Docker itegration 2020-12-06 01:41:36 -07:00
Ganesh Gore 60060762e5 [Action] Replaced destination repo url 2020-12-06 01:41:00 -07:00
Ganesh Gore 2ecc166e95 [Action] Added destination repo push action 2020-12-06 01:40:38 -07:00
Ganesh Gore 8105a46f07 [Actions] Alternate option to modify file 2020-12-06 01:40:21 -07:00
Ganesh Gore d63dfa00b7 [Actions] filename bugfix 2020-12-06 01:40:21 -07:00
Ganesh Gore 027f0f76a2 [bugfix] Indentation bug in actions yaml 2020-12-06 01:40:21 -07:00
Ganesh Gore 41f2844698 [Action] And modify file and push action 2020-12-06 01:40:21 -07:00
Ganesh Gore 62e0cffea1 [Actions] Disables build test in ganesh_dev branch 2020-12-06 01:40:21 -07:00
Ganesh Gore d5a5ec5b1d [Actions] Testing repository fetch option 2020-12-06 01:40:21 -07:00
Ganesh Gore 452af85e98 [Cleanup] Removed/Ignored testbench files from generated source 2020-12-06 01:40:21 -07:00
tangxifan f5c1d9c0a0 [Arch] enable local encoders 2020-12-06 01:40:21 -07:00
tangxifan ad120e205b [CI] Add new arch to CI test 2020-12-06 01:40:21 -07:00
tangxifan 004f9dbcca [Arch] Bug fix in new arch 2020-12-06 01:40:21 -07:00
tangxifan c015d65a03 [Script] Add task run for custom cell FPGA architectures 2020-12-06 01:40:21 -07:00
tangxifan 4ddc6955a3 [Arch] Add architecture using custom cells 2020-12-06 01:40:21 -07:00
tangxifan 22451870dd [CI] Patch github repo path to sync with OpenFPGA repo movement 2020-12-06 01:39:16 -07:00
tangxifan 87f79d78bb [CI] Add wrapper generator examples to CI 2020-12-06 01:39:16 -07:00
tangxifan 696529b43d [Script] Increase routing chan width from 40 to 60 for version 1.2 2020-12-06 01:39:16 -07:00
Laboratory for Nano Integrated Systems (LNIS) f572be8fc2
Merge pull request #56 from lnis-uofu/xt_dev 
Python script to adapt OpenFPGA netlist to use custom MUX cells
 2020-12-05 22:11:36 -07:00
tangxifan 443eb12710 [CI] Add test to CI 2020-12-05 21:17:59 -07:00
tangxifan 22f2b3aa90 [HDL] Add python script to adapt OpenFPGA MUX primitives to use custom cells 2020-12-05 21:14:56 -07:00
tangxifan 6039ae92ca [Arch] Bug fix for buffering two-level routing multiplexers using custom cells 2020-12-05 19:37:34 -07:00
Laboratory for Nano Integrated Systems (LNIS) 52413059f6
Merge pull request #55 from lnis-uofu/xt_dev 
Major Changes in Documentation
 2020-12-04 14:47:52 -07:00
tangxifan 3a75e079ba [Doc] Update the frontpage README 2020-12-04 14:09:40 -07:00
tangxifan f766052bf7 [Doc] Add route W to device comparison 2020-12-04 13:41:47 -07:00
tangxifan 156e1d007c [Doc] Add missing figure and bug fix 2020-12-04 13:34:41 -07:00
tangxifan 1948f000e0 [Doc] Reorganize documentation for SOFA HD device family 2020-12-04 12:02:30 -07:00
tangxifan 6fca7b9641 [Doc] Add figures about fle architecture v1.1 2020-12-04 09:27:11 -07:00
Laboratory for Nano Integrated Systems (LNIS) a09933cb75
Merge pull request #54 from lnis-uofu/xt_dev 
Critical Patches on Simulation Scripts and Testbenches
 2020-12-03 17:20:02 -07:00
tangxifan 51167f871e [Testbench] Patch ccff test 2020-12-02 20:07:36 -07:00
tangxifan ce058447f2 [MSIM] Bug fix in reporting errors 2020-12-02 20:07:16 -07:00
tangxifan 2db2b468fe [Script] Try auto number of simulation clock cycles 2020-12-02 19:33:28 -07:00
tangxifan 3a097b38af [CI] Remove the out-of-data tests 2020-12-02 18:00:48 -07:00
tangxifan 930f7ec486 [Script] Remove task run for redundant architectures 2020-12-02 17:56:58 -07:00
tangxifan 7b637e6676 [Testbench] Bug fix in post PnR testbench templates 2020-12-02 17:50:49 -07:00
tangxifan b966829566 [Script] Force a fixed number of clock cycles in simulation to avoid false-positive 2020-12-02 17:50:23 -07:00
tangxifan a19c9bdbda [CI] Add CCFF and SCFF testbench conversion to CI test 2020-12-02 15:30:54 -07:00
tangxifan 6814b3bb60 [Testbench] Now ccff and scff testbench template have multiple versions corresponding to the FPGA variants 2020-12-02 15:22:19 -07:00
tangxifan 4875b2de95 [HDL] Patch pin assignment names to be consistent with post-PnR netlists 2020-12-02 14:02:18 -07:00
tangxifan 06731e092e [Arch] Patch reset port name to be consistent with post-PnR netlist 2020-12-02 13:46:40 -07:00
tangxifan 20cba3f558 [Testbench] Add testbench for post-PnR verification for FPGA with reset 2020-12-02 13:43:06 -07:00
tangxifan ea3165b14d Merge branch 'master' into xt_dev 2020-12-02 13:27:50 -07:00
tangxifan b9053269e9
Merge pull request #52 from lnis-uofu/ganesh_dev 
Ganesh dev
 2020-12-02 13:10:35 -07:00
Ganesh Gore 0cc5b492d2 [Cleanup] Removed/Ignored testbench files from generated source 2020-12-02 12:03:24 -07:00
tangxifan 61163de580 [Testbench] Correct path to post-pnR netlists and prepare for sign-off on FPGA with reset 2020-12-02 12:00:28 -07:00
Ganesh Gore 361cd2d9e1 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-12-02 10:56:59 -07:00