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303 Commits 16 Branches 1 Tag 1.8 GiB
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303 Commits

Author SHA1 Message Date
tangxifan 16af5e6ad8 [Arch] Minor change to keep a regular arch in fle->lut connection 2020-11-09 15:52:46 -07:00
tangxifan 1b2cf27c2a [Testbench] Update post-PnR testbench with latest PnRed netlists 2020-11-09 15:12:32 -07:00
tangxifan 630c4060a8 [Arch] Detect some bugs (will not cause verification failed) in vpr arch 2020-11-09 15:12:00 -07:00
tangxifan 69afafb581
Merge pull request #14 from LNIS-Projects/ganesh_dev 
Ganesh dev
 2020-11-09 09:04:27 -07:00
Laboratory for Nano Integrated Systems (LNIS) dbe8c73bdb
Merge pull request #13 from LNIS-Projects/xt_dev 
Misc Updates: Caravel User Project Wrapper, Post-PnR Testbench and STA script
 2020-11-09 08:48:49 -07:00
Ganesh Gore 015c67e10f Added clock feedthroughs 2020-11-08 18:37:55 -07:00
tangxifan b2867de8b4 [SNPS_PT] fine-tune script for SDF output directory 2020-11-08 16:35:35 -07:00
tangxifan 0195c1601a [Doc] Add readme to SDF dir 2020-11-08 16:35:10 -07:00
tangxifan 802d72a606 [SNPS_PT] Add template script to generate SDF from post-PnR netlists 2020-11-08 16:31:33 -07:00
tangxifan 536494c0d4 [Doc] Add Synopsys PrimeTime readme 2020-11-08 16:31:08 -07:00
tangxifan 17e30c55bf [Testbench] Bug fix in the post-pnr testbench 2020-11-08 14:25:49 -07:00
tangxifan 11ee81f8c4 [Arch] Bug fix in the caravel arch 2020-11-08 14:25:38 -07:00
tangxifan 72db7fc7c0 [Script] Adapt openfpga task-run configuration to use the fabric key scripts 2020-11-08 11:47:08 -07:00
tangxifan 6e254356d1 [Script] Add openfpga script template using fabric key 2020-11-08 11:46:46 -07:00
tangxifan 309c63513a [Script] Add example openfpga-run scripts using fabric key 2020-11-08 11:41:07 -07:00
tangxifan 2683bdd0ae [HDL] Add Post-PnR testbench 2020-11-08 11:36:18 -07:00
tangxifan 795b958239 [Arch] Add fabric key for 2x2 fabric 2020-11-08 11:35:59 -07:00
tangxifan 25ada3f6a0 Merge branch 'master' into xt_dev 2020-11-08 10:22:18 -07:00
Ganesh Gore 229b8e22b4 Fixed scan-chain connections 2020-11-08 01:06:13 -07:00
tangxifan ae97e4424d [HDL] Add wrapper for Caravel interface 2020-11-07 22:42:29 -07:00
tangxifan 26951dad45
Merge pull request #12 from LNIS-Projects/ganesh_dev 
Ganesh dev
 2020-11-07 20:40:09 -07:00
Ganesh Gore 31a73a42ba Updated design with new architecure and merged grid_io 2020-11-06 22:35:31 -07:00
tangxifan a36cc83280
Merge pull request #11 from LNIS-Projects/xt_dev 
[Arch] Use single-output DFF to further compress area
 2020-11-06 15:15:52 -07:00
tangxifan 8d84d83eab [Arch] Use single-output DFF to further compress area 2020-11-06 11:47:31 -07:00
Laboratory for Nano Integrated Systems (LNIS) d9cbaa3eec
Merge pull request #10 from LNIS-Projects/xt_dev 
Patch to have UNIQUE routing blocks
 2020-11-05 22:23:50 -07:00
tangxifan 6811604e5c [Arch] Revert back to a lower Fc for area efficiency 2020-11-05 22:23:11 -07:00
tangxifan fe3bf8ba58 [Arch] Patch to have UNIQUE routing blocks 2020-11-05 22:20:51 -07:00
Laboratory for Nano Integrated Systems (LNIS) 2ed8bee461
Merge pull request #9 from LNIS-Projects/xt_dev 
Minor patch on arch for Caravel to force unique CBY
 2020-11-05 21:58:08 -07:00
tangxifan 1892dd5205 [Arch] Minor patch on arch to force unique CBY 2020-11-05 21:55:43 -07:00
Laboratory for Nano Integrated Systems (LNIS) e6c51dbb42
Merge pull request #8 from LNIS-Projects/xt_dev 
Addition of Architectures Tuned for Caravel SoC Interface
 2020-11-05 15:19:39 -07:00
tangxifan e952eb951d [HDL] Add preprocessing flags for running functional verification 2020-11-05 11:29:23 -07:00
tangxifan 6b474ce422 [Arch] Patch openfpga arch for new syntax on I/O 2020-11-05 10:37:37 -07:00
tangxifan bbdd13ac16 [Script] Add openfpga task run for caravel architecture 2020-11-05 10:25:23 -07:00
tangxifan a25b8252f3 [Arch] Add openfpga arch template for the caravel 2020-11-05 10:20:54 -07:00
tangxifan 64d1113461 [HDL] Add HDL codes for the FPGA I/O cell tuned for Caravel 2020-11-05 10:18:52 -07:00
tangxifan 5b69b0a087 [Arch] Add the VPR architecture tuned for Caravel I/O interface 2020-11-05 09:43:38 -07:00
Ganesh Gore 89d42cc03d Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-11-03 13:15:24 -07:00
Laboratory for Nano Integrated Systems (LNIS) 04615e0709
Merge pull request #7 from LNIS-Projects/xt_dev 
Add Architecture with pure digital I/O for Embedded FPGA Fabric
 2020-11-03 10:10:29 -07:00
tangxifan 1264054cab [Arch] Bug fix in netlist path 2020-11-03 09:57:25 -07:00
tangxifan 48d8f8b664 [Arch] Same patch on the scff on another arch 2020-11-03 09:54:30 -07:00
tangxifan 533a6ab90f [Arch] Use an exact fit scan-chain flip-flop in the architectures 2020-11-03 09:53:16 -07:00
tangxifan a46d1bd492 [Doc] Add README to SDC and Testbench directories 2020-11-03 09:27:06 -07:00
tangxifan 8702073354 [Doc] Add readme for HDL directory 2020-11-03 09:23:33 -07:00
tangxifan 12881d7a31 [HDL] Move verilog wrapper to HDL directory 2020-11-03 09:19:43 -07:00
tangxifan b5c781f555 [Arch] Patch the HDL netlist name to differetiate between cell types 2020-11-03 09:17:22 -07:00
tangxifan 40ca8dfbe3 [Arch] Update architecture files to use the wrapper files 2020-11-03 09:14:47 -07:00
tangxifan b67896a225 [HDL] Add embedded I/O HDL wrapper using the high density cells 2020-11-03 09:05:20 -07:00
tangxifan 0958d9c50f [Script] Add openfpga task run for embedded architecture 2020-11-02 20:09:35 -07:00
tangxifan c26f8a5aac [Arch] Add architecture files for embedded FPGA IP 2020-11-02 19:55:40 -07:00
Laboratory for Nano Integrated Systems (LNIS) 42589c96b7
Merge pull request #6 from LNIS-Projects/xt_dev 
Bug fix in the k4 architecture that blocks verification
 2020-11-02 18:49:15 -07:00