mirror of https://github.com/lnis-uofu/SOFA.git
Added clock feedthroughs
This commit is contained in:
Ganesh Gore
parent
229b8e22b4
commit
015c67e10f
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@ -1,176 +0,0 @@
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//
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`timescale 1ns / 1ps
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//
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//
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module grid_io_bottom(prog_clk,
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gfpga_pad_EMBEDDED_IO_SOC_IN,
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gfpga_pad_EMBEDDED_IO_SOC_OUT,
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gfpga_pad_EMBEDDED_IO_SOC_DIR,
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top_width_0_height_0__pin_0_,
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top_width_0_height_0__pin_2_,
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top_width_0_height_0__pin_4_,
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top_width_0_height_0__pin_6_,
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top_width_0_height_0__pin_8_,
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top_width_0_height_0__pin_10_,
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ccff_head,
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top_width_0_height_0__pin_1_upper,
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top_width_0_height_0__pin_1_lower,
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top_width_0_height_0__pin_3_upper,
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top_width_0_height_0__pin_3_lower,
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top_width_0_height_0__pin_5_upper,
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top_width_0_height_0__pin_5_lower,
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top_width_0_height_0__pin_7_upper,
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top_width_0_height_0__pin_7_lower,
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top_width_0_height_0__pin_9_upper,
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top_width_0_height_0__pin_9_lower,
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top_width_0_height_0__pin_11_upper,
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top_width_0_height_0__pin_11_lower,
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ccff_tail);
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//
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input [0:0] prog_clk;
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//
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input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN;
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//
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output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT;
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//
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output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR;
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//
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input [0:0] top_width_0_height_0__pin_0_;
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//
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input [0:0] top_width_0_height_0__pin_2_;
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//
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input [0:0] top_width_0_height_0__pin_4_;
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//
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input [0:0] top_width_0_height_0__pin_6_;
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//
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input [0:0] top_width_0_height_0__pin_8_;
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//
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input [0:0] top_width_0_height_0__pin_10_;
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//
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input [0:0] ccff_head;
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//
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output [0:0] top_width_0_height_0__pin_1_upper;
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//
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output [0:0] top_width_0_height_0__pin_1_lower;
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//
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output [0:0] top_width_0_height_0__pin_3_upper;
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//
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output [0:0] top_width_0_height_0__pin_3_lower;
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//
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output [0:0] top_width_0_height_0__pin_5_upper;
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//
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output [0:0] top_width_0_height_0__pin_5_lower;
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//
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output [0:0] top_width_0_height_0__pin_7_upper;
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//
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output [0:0] top_width_0_height_0__pin_7_lower;
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//
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output [0:0] top_width_0_height_0__pin_9_upper;
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//
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output [0:0] top_width_0_height_0__pin_9_lower;
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//
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output [0:0] top_width_0_height_0__pin_11_upper;
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//
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output [0:0] top_width_0_height_0__pin_11_lower;
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//
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output [0:0] ccff_tail;
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//
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//
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//
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//
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wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
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wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
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wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
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wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
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wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
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//
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//
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//
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assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0];
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assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0];
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assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0];
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assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0];
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assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0];
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assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0];
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//
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logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
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.prog_clk(prog_clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
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.io_outpad(top_width_0_height_0__pin_0_[0]),
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.ccff_head(ccff_head[0]),
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.io_inpad(top_width_0_height_0__pin_1_upper[0]),
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.ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0]));
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logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
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.prog_clk(prog_clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]),
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.io_outpad(top_width_0_height_0__pin_2_[0]),
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.ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]),
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.io_inpad(top_width_0_height_0__pin_3_upper[0]),
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.ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0]));
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logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
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.prog_clk(prog_clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]),
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.io_outpad(top_width_0_height_0__pin_4_[0]),
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.ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]),
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.io_inpad(top_width_0_height_0__pin_5_upper[0]),
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.ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0]));
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logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
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.prog_clk(prog_clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]),
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.io_outpad(top_width_0_height_0__pin_6_[0]),
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.ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]),
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.io_inpad(top_width_0_height_0__pin_7_upper[0]),
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.ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0]));
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logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
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.prog_clk(prog_clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]),
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.io_outpad(top_width_0_height_0__pin_8_[0]),
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.ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]),
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.io_inpad(top_width_0_height_0__pin_9_upper[0]),
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.ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0]));
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logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
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.prog_clk(prog_clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[5]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]),
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.io_outpad(top_width_0_height_0__pin_10_[0]),
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.ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]),
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.io_inpad(top_width_0_height_0__pin_11_upper[0]),
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.ccff_tail(ccff_tail[0]));
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endmodule
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//
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//
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@ -1,71 +0,0 @@
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//
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//
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//
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//
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//
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//
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//
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//
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`timescale 1ns / 1ps
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//
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//
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module grid_io_left(prog_clk,
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gfpga_pad_EMBEDDED_IO_SOC_IN,
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gfpga_pad_EMBEDDED_IO_SOC_OUT,
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gfpga_pad_EMBEDDED_IO_SOC_DIR,
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right_width_0_height_0__pin_0_,
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ccff_head,
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right_width_0_height_0__pin_1_upper,
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right_width_0_height_0__pin_1_lower,
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ccff_tail);
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//
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input [0:0] prog_clk;
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//
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input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
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//
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output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
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//
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output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
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//
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input [0:0] right_width_0_height_0__pin_0_;
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//
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input [0:0] ccff_head;
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//
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output [0:0] right_width_0_height_0__pin_1_upper;
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//
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output [0:0] right_width_0_height_0__pin_1_lower;
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//
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output [0:0] ccff_tail;
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//
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//
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//
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//
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//
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//
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//
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assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0];
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//
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logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
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.prog_clk(prog_clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
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.io_outpad(right_width_0_height_0__pin_0_[0]),
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.ccff_head(ccff_head[0]),
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.io_inpad(right_width_0_height_0__pin_1_upper[0]),
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.ccff_tail(ccff_tail[0]));
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endmodule
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//
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//
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@ -1,71 +0,0 @@
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//
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//
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//
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//
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//
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//
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//
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//
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`timescale 1ns / 1ps
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//
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//
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module grid_io_right(prog_clk,
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gfpga_pad_EMBEDDED_IO_SOC_IN,
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gfpga_pad_EMBEDDED_IO_SOC_OUT,
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gfpga_pad_EMBEDDED_IO_SOC_DIR,
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left_width_0_height_0__pin_0_,
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ccff_head,
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left_width_0_height_0__pin_1_upper,
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left_width_0_height_0__pin_1_lower,
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ccff_tail);
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//
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input [0:0] prog_clk;
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//
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input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
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//
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output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
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//
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output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
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//
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input [0:0] left_width_0_height_0__pin_0_;
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//
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input [0:0] ccff_head;
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//
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output [0:0] left_width_0_height_0__pin_1_upper;
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//
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output [0:0] left_width_0_height_0__pin_1_lower;
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//
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output [0:0] ccff_tail;
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//
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//
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//
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//
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//
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//
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//
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assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0];
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//
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logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
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.prog_clk(prog_clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
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.io_outpad(left_width_0_height_0__pin_0_[0]),
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.ccff_head(ccff_head[0]),
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.io_inpad(left_width_0_height_0__pin_1_upper[0]),
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.ccff_tail(ccff_tail[0]));
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endmodule
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//
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//
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@ -1,71 +0,0 @@
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//
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//
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//
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//
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//
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//
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//
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//
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`timescale 1ns / 1ps
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//
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//
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module grid_io_top(prog_clk,
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gfpga_pad_EMBEDDED_IO_SOC_IN,
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gfpga_pad_EMBEDDED_IO_SOC_OUT,
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gfpga_pad_EMBEDDED_IO_SOC_DIR,
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bottom_width_0_height_0__pin_0_,
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ccff_head,
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bottom_width_0_height_0__pin_1_upper,
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bottom_width_0_height_0__pin_1_lower,
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ccff_tail);
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//
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input [0:0] prog_clk;
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//
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input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
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//
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output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
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//
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output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
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//
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input [0:0] bottom_width_0_height_0__pin_0_;
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//
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input [0:0] ccff_head;
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//
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output [0:0] bottom_width_0_height_0__pin_1_upper;
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//
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output [0:0] bottom_width_0_height_0__pin_1_lower;
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//
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output [0:0] ccff_tail;
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//
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//
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//
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//
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//
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//
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//
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assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0];
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//
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logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
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.prog_clk(prog_clk[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
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.io_outpad(bottom_width_0_height_0__pin_0_[0]),
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.ccff_head(ccff_head[0]),
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.io_inpad(bottom_width_0_height_0__pin_1_upper[0]),
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.ccff_tail(ccff_tail[0]));
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endmodule
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//
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//
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@ -178,7 +178,7 @@ module cbx_1__0_
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(
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.prog_clk(prog_clk[0]),
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.ccff_head(ccff_head[0]),
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.ccff_tail(ccff_tail_mid),
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.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -189,7 +189,7 @@ module cbx_1__0_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -200,7 +200,7 @@ module cbx_1__0_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -211,7 +211,7 @@ module cbx_1__0_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -222,7 +222,7 @@ module cbx_1__0_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
|
||||
);
|
||||
|
|
|
|||
|
|
@ -227,7 +227,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -238,7 +238,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -249,7 +249,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -260,7 +260,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -271,7 +271,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -282,7 +282,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -293,7 +293,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -304,7 +304,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -406,7 +406,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -417,7 +417,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -428,7 +428,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -439,7 +439,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -450,7 +450,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -461,7 +461,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -472,7 +472,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -483,7 +483,7 @@ module cbx_1__2_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
|
||||
);
|
||||
|
|
|
|||
|
|
@ -221,7 +221,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -232,7 +232,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -243,7 +243,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -254,7 +254,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -265,7 +265,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -276,7 +276,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -287,7 +287,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -298,7 +298,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -400,7 +400,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -411,7 +411,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -422,7 +422,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -433,7 +433,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -444,7 +444,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -455,7 +455,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -466,7 +466,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
|
||||
);
|
||||
|
|
@ -477,7 +477,7 @@ module cby_2__1_
|
|||
(
|
||||
.prog_clk(prog_clk[0]),
|
||||
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
|
||||
.ccff_tail(ccff_tail_mid),
|
||||
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
|
||||
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
|
||||
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
|
||||
);
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
module GPIO (A, IE, OE, Y, in, out, mem_out);
|
||||
output A;
|
||||
output IE;
|
||||
output OE;
|
||||
output Y;
|
||||
input in;
|
||||
output out;
|
||||
input mem_out;
|
||||
|
||||
assign A = in;
|
||||
assign out = Y;
|
||||
assign IE = mem_out;
|
||||
sky130_fd_sc_hd__inv_1 ie_oe_inv (
|
||||
.A (mem_out),
|
||||
.Y (OE) );
|
||||
endmodule
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
- Fabric bitstream
|
||||
- Author: Xifan TANG
|
||||
- Organization: University of Utah
|
||||
- Date: Sat Nov 7 21:20:25 2020
|
||||
- Date: Sun Nov 8 17:53:57 2020
|
||||
-->
|
||||
|
||||
<fabric_bitstream>
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
- Architecture independent bitstream
|
||||
- Author: Xifan TANG
|
||||
- Organization: University of Utah
|
||||
- Date: Sat Nov 7 21:20:25 2020
|
||||
- Date: Sun Nov 8 17:53:56 2020
|
||||
-->
|
||||
|
||||
<bitstream_block name="fpga_top" hierarchy_level="0">
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock
|
|||
Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
|
||||
Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
|
||||
Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
|
||||
# Loading Architecture Description took 0.01 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB)
|
||||
# Loading Architecture Description took 0.00 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB)
|
||||
# Building complex block graph
|
||||
Warning 6: [LINE 582] false logically-equivalent pin clb[0].I0[1].
|
||||
Warning 7: [LINE 582] false logically-equivalent pin clb[0].I0[2].
|
||||
|
|
@ -83,7 +83,7 @@ Warning 18: [LINE 618] false logically-equivalent pin clb[0].I6[1].
|
|||
Warning 19: [LINE 618] false logically-equivalent pin clb[0].I6[2].
|
||||
Warning 20: [LINE 624] false logically-equivalent pin clb[0].I7[1].
|
||||
Warning 21: [LINE 624] false logically-equivalent pin clb[0].I7[2].
|
||||
# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB)
|
||||
# Building complex block graph took 0.00 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB)
|
||||
# Load circuit
|
||||
# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB)
|
||||
# Clean circuit
|
||||
|
|
@ -250,14 +250,14 @@ Device Utilization: 0.25 (target 1.00)
|
|||
|
||||
Netlist conversion complete.
|
||||
|
||||
# Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB)
|
||||
# Packing took 0.00 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB)
|
||||
# Load Packing
|
||||
Begin loading packed FPGA netlist file.
|
||||
Netlist generated from file 'top.net'.
|
||||
Detected 0 constant generators (to see names run with higher pack verbosity)
|
||||
Finished loading packed FPGA netlist file (took 0.02 seconds).
|
||||
Finished loading packed FPGA netlist file (took 0 seconds).
|
||||
Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
|
||||
# Load Packing took 0.02 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB)
|
||||
# Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB)
|
||||
Warning 35: Netlist contains 0 global net to non-global architecture pin connections
|
||||
|
||||
Netlist num_nets: 3
|
||||
|
|
@ -301,7 +301,7 @@ Device Utilization: 0.25 (target 1.00)
|
|||
Physical Tile clb:
|
||||
Block Utilization: 0.25 Logical Block: clb
|
||||
|
||||
## Build Device Grid took 0.00 seconds (max_rss 10.7 MiB, delta_rss +0.0 MiB)
|
||||
## Build Device Grid took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
## Build tileable routing resource graph
|
||||
X-direction routing channel width is 40
|
||||
Y-direction routing channel width is 40
|
||||
|
|
@ -309,10 +309,10 @@ Warning 40: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pi
|
|||
Warning 41: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||||
Warning 42: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
|
||||
Warning 43: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||||
## Build tileable routing resource graph took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB)
|
||||
## Build tileable routing resource graph took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
RR Graph Nodes: 756
|
||||
RR Graph Edges: 2930
|
||||
# Create Device took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB)
|
||||
# Create Device took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
# Placement
|
||||
## Computing placement delta delay look-up
|
||||
|
|
@ -321,12 +321,12 @@ Warning 44: in check_rr_node: RR node: 119 type: OPIN location: (1,1) pin: 50 pi
|
|||
Warning 45: in check_rr_node: RR node: 120 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||||
Warning 46: in check_rr_node: RR node: 327 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
|
||||
Warning 47: in check_rr_node: RR node: 328 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||||
### Build routing resource graph took 0.00 seconds (max_rss 11.2 MiB, delta_rss +0.0 MiB)
|
||||
### Build routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
RR Graph Nodes: 756
|
||||
RR Graph Edges: 2428
|
||||
### Computing delta delays
|
||||
### Computing delta delays took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.0 MiB)
|
||||
## Computing placement delta delay look-up took 0.01 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB)
|
||||
### Computing delta delays took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
## Computing placement delta delay look-up took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
There are 3 point to point connections in this circuit.
|
||||
|
||||
|
|
@ -440,7 +440,7 @@ Placement total # of swap attempts: 292
|
|||
Swaps aborted : 0 ( 0.0 %)
|
||||
|
||||
Aborted Move Reasons:
|
||||
# Placement took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.5 MiB)
|
||||
# Placement took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
# Routing
|
||||
## Build tileable routing resource graph
|
||||
|
|
@ -450,7 +450,7 @@ Warning 48: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pi
|
|||
Warning 49: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||||
Warning 50: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
|
||||
Warning 51: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||||
## Build tileable routing resource graph took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.0 MiB)
|
||||
## Build tileable routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
RR Graph Nodes: 756
|
||||
RR Graph Edges: 2930
|
||||
Confirming router algorithm: TIMING_DRIVEN.
|
||||
|
|
@ -464,7 +464,7 @@ Restoring best routing
|
|||
Critical path: 0.86731 ns
|
||||
Successfully routed after 2 routing iterations.
|
||||
Router Stats: total_nets_routed: 4 total_connections_routed: 4 total_heap_pushes: 289 total_heap_pops: 187
|
||||
# Routing took 0.01 seconds (max_rss 11.9 MiB, delta_rss +0.2 MiB)
|
||||
# Routing took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Checking to ensure routing is legal...
|
||||
Completed routing consistency check successfully.
|
||||
|
|
@ -562,9 +562,9 @@ Setup slack histogram:
|
|||
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
|
||||
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
|
||||
|
||||
Timing analysis took 0.000465 seconds (0.000410914 STA, 5.4086e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined).
|
||||
Timing analysis took 0.000351611 seconds (0.000312774 STA, 3.8837e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined).
|
||||
VPR suceeded
|
||||
The entire flow of VPR took 0.10 seconds (max_rss 11.9 MiB)
|
||||
The entire flow of VPR took 0.07 seconds (max_rss 12.7 MiB)
|
||||
|
||||
Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
|
||||
|
||||
|
|
@ -578,10 +578,10 @@ Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be def
|
|||
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree' port 'sram')
|
||||
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree_tapbuf' port 'sram')
|
||||
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'frac_lut4' port 'sram')
|
||||
Read OpenFPGA architecture took 0.00 seconds (max_rss 12.0 MiB, delta_rss +0.1 MiB)
|
||||
Read OpenFPGA architecture took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
Check circuit library
|
||||
Checking circuit library passed.
|
||||
Check circuit library took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
|
||||
Check circuit library took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
Found 0 errors when checking configurable memory circuit models!
|
||||
|
||||
Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
|
|
@ -590,7 +590,7 @@ Confirm selected options when call command 'read_openfpga_simulation_setting':
|
|||
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
|
||||
Read OpenFPGA simulation settings
|
||||
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
|
||||
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges
|
||||
|
||||
|
|
@ -633,7 +633,7 @@ Done with 18 nodes mapping
|
|||
[88%] Backannotated GSB[2][1]
|
||||
[100%] Backannotated GSB[2][2]
|
||||
Backannotated 9 General Switch Blocks (GSBs).
|
||||
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
|
||||
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
|
||||
[11%] Sorted edges for GSB[0][0]
|
||||
[22%] Sorted edges for GSB[0][1]
|
||||
|
|
@ -645,14 +645,14 @@ Backannotated 9 General Switch Blocks (GSBs).
|
|||
[88%] Sorted edges for GSB[2][1]
|
||||
[100%] Sorted edges for GSB[2][2]
|
||||
Sorted edges for 9 General Switch Blocks (GSBs).
|
||||
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
|
||||
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
# Build a library of physical multiplexers
|
||||
Built a multiplexer library of 15 physical multiplexers.
|
||||
Maximum multiplexer size is 17.
|
||||
# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB)
|
||||
# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
# Build the annotation about direct connection between tiles
|
||||
Built 6 tile-to-tile direct connections
|
||||
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB)
|
||||
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
Building annotation for mapped blocks on grid locations...Done
|
||||
User specified the operating clock frequency to use VPR results
|
||||
Use VPR critical path delay 1.04077e-18 [ns] with a 20 [%] slack in OpenFPGA.
|
||||
|
|
@ -662,7 +662,7 @@ Average net density: 0.42
|
|||
Median net density: 0.00
|
||||
Average net density after weighting: 0.42
|
||||
Will apply 2 operating clock cycles to simulations
|
||||
Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.3 MiB)
|
||||
Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml
|
||||
|
||||
|
|
@ -676,7 +676,7 @@ Confirm selected options when call command 'build_fabric':
|
|||
--verbose: off
|
||||
Identify unique General Switch Blocks (GSBs)
|
||||
Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%)
|
||||
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB)
|
||||
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Read Fabric Key
|
||||
Read Fabric Key took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
|
|
@ -691,7 +691,7 @@ Build fabric module graph
|
|||
# Build local encoder (for multiplexers) modules
|
||||
# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
|
||||
# Building multiplexer modules
|
||||
# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB)
|
||||
# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.2 MiB)
|
||||
# Build Look-Up Table (LUT) modules
|
||||
# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.3 MiB)
|
||||
# Build wire modules
|
||||
|
|
@ -703,7 +703,7 @@ Building logical tiles...Done
|
|||
Building physical tiles...Done
|
||||
# Build grid modules took 0.00 seconds (max_rss 13.7 MiB, delta_rss +0.5 MiB)
|
||||
# Build unique routing modules...
|
||||
# Build unique routing modules... took 0.02 seconds (max_rss 16.5 MiB, delta_rss +2.8 MiB)
|
||||
# Build unique routing modules... took 0.01 seconds (max_rss 16.5 MiB, delta_rss +2.8 MiB)
|
||||
# Build FPGA fabric module
|
||||
## Add grid instances to top module
|
||||
## Add grid instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
|
||||
|
|
@ -720,7 +720,7 @@ Building physical tiles...Done
|
|||
## Add module nets for configuration buses
|
||||
## Add module nets for configuration buses took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
|
||||
# Build FPGA fabric module took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.8 MiB)
|
||||
Build fabric module graph took 0.03 seconds (max_rss 17.3 MiB, delta_rss +4.6 MiB)
|
||||
Build fabric module graph took 0.02 seconds (max_rss 17.3 MiB, delta_rss +4.6 MiB)
|
||||
Create I/O location mapping for top module
|
||||
Create I/O location mapping for top module took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
|
|
@ -729,13 +729,13 @@ Command line to execute: repack
|
|||
Confirm selected options when call command 'repack':
|
||||
--verbose: off
|
||||
Build routing resource graph for the physical implementation of logical tile
|
||||
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.5 MiB, delta_rss +0.3 MiB)
|
||||
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB)
|
||||
Repack clustered blocks to physical implementation of logical tile
|
||||
Repack clustered block 'c'...Done
|
||||
Repack clustered block 'out:c'...Done
|
||||
Repack clustered block 'a'...Done
|
||||
Repack clustered block 'b'...Done
|
||||
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.5 MiB, delta_rss +0.0 MiB)
|
||||
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB)
|
||||
Build truth tables for physical LUTs
|
||||
Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.8 MiB, delta_rss +0.3 MiB)
|
||||
|
||||
|
|
@ -756,7 +756,7 @@ Build fabric-independent bitstream for implementation 'top'
|
|||
took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
|
||||
Warning 56: Directory path is empty and nothing will be created.
|
||||
Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
|
||||
Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.03 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
|
||||
Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.02 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: build_fabric_bitstream
|
||||
|
||||
|
|
@ -849,7 +849,7 @@ Building physical tiles...Done
|
|||
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
|
||||
Written 73 Verilog modules in total
|
||||
Write Verilog netlists for FPGA fabric
|
||||
took 0.19 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB)
|
||||
took 0.17 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB)
|
||||
|
||||
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
|
||||
|
||||
|
|
@ -869,7 +869,7 @@ Write Verilog testbenches for FPGA fabric
|
|||
|
||||
Warning 60: Directory './SRC' already exists. Will overwrite contents
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top'
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.02 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
|
||||
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
|
||||
|
|
@ -879,7 +879,7 @@ Succeed to create directory './SimulationDeck'
|
|||
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
|
||||
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
Write Verilog testbenches for FPGA fabric
|
||||
took 0.05 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
took 0.03 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: exit
|
||||
|
||||
|
|
@ -887,6 +887,6 @@ Confirm selected options when call command 'exit':
|
|||
|
||||
Finish execution with 0 errors
|
||||
|
||||
The entire OpenFPGA flow took 0.29 seconds
|
||||
The entire OpenFPGA flow took 0.19 seconds
|
||||
|
||||
Thank you for using OpenFPGA!
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
module GPIO (A, IE, OE, Y, in, out, mem_out);
|
||||
output A;
|
||||
output IE;
|
||||
output OE;
|
||||
output Y;
|
||||
input in;
|
||||
output out;
|
||||
input mem_out;
|
||||
|
||||
assign A = in;
|
||||
assign out = Y;
|
||||
assign IE = mem_out;
|
||||
sky130_fd_sc_hd__inv_1 ie_oe_inv (
|
||||
.A (mem_out),
|
||||
.Y (OE) );
|
||||
endmodule
|
||||
|
|
@ -5,11 +5,12 @@ FPGA22_HIER_SKY_PNR
|
|||
|
||||
Updates
|
||||
-------------------
|
||||
- **Merged `grid_io` modules with connection blocks**
|
||||
- **Pre-routed scan chain signals**
|
||||
- **Created `carry_chain` feedthrough between `grid_clb` modules**
|
||||
- Prerouting global signals (`Test_en`)
|
||||
- Prerouting clock signals
|
||||
- Merged `grid_io` modules with connection blocks
|
||||
- Pre-routed scan chain signals
|
||||
- Created `carry_chain` feedthrough between `grid_clb` modules
|
||||
- **Prerouting global signals (`Test_en`)**
|
||||
- **Prerouting clock signals**
|
||||
- **Enabled Feed through generation for clock**
|
||||
|
||||
Directory Structure
|
||||
-------------------
|
||||
|
|
|
|||
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|
Before Width: | Height: | Size: 85 KiB After Width: | Height: | Size: 97 KiB |
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Load Diff
BIN
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds (Stored with Git LFS)
BIN
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds (Stored with Git LFS)
Binary file not shown.
File diff suppressed because it is too large
Load Diff
BIN
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef (Stored with Git LFS)
BIN
FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef (Stored with Git LFS)
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Load Diff
|
|
@ -1,18 +1,18 @@
|
|||
| Module | Util| Area| Sites| Insts| Std_Cells
|
||||
|--------------------|----------|-----------------|-------|-------|-------
|
||||
| sb_0__0_ | 39.51 | 6426.163200 | 5136 | 1 | 93
|
||||
| sb_0__1_ | 67.8 | 7086.796800 | 5664 | 1 | 119
|
||||
| sb_0__2_ | 41.69 | 6426.163200 | 5136 | 1 | 83
|
||||
| sb_1__0_ | 61.56 | 8227.891200 | 6576 | 1 | 132
|
||||
| sb_1__1_ | 81.35 | 8888.524800 | 7104 | 1 | 116
|
||||
| sb_1__2_ | 65.88 | 8227.891200 | 6576 | 1 | 133
|
||||
| sb_2__0_ | 56.8 | 6426.163200 | 5136 | 1 | 103
|
||||
| sb_2__1_ | 76.61 | 7086.796800 | 5664 | 1 | 109
|
||||
| sb_2__2_ | 59.11 | 6426.163200 | 5136 | 1 | 89
|
||||
| cbx_1__0_ | 65.82 | 4444.262400 | 3552 | 2 | 115
|
||||
| cbx_1__1_ | 70.58 | 4444.262400 | 3552 | 2 | 36
|
||||
| cbx_1__2_ | 75.73 | 4444.262400 | 3552 | 2 | 38
|
||||
| cby_0__1_ | 31.85 | 4624.435200 | 3696 | 2 | 100
|
||||
| cby_1__1_ | 66.96 | 4624.435200 | 3696 | 2 | 34
|
||||
| cby_2__1_ | 72.89 | 4624.435200 | 3696 | 2 | 38
|
||||
| grid_clb_1__1_ | 76.09 | 12071.577600 | 9648 | 4 | 63
|
||||
| sb_0__0_ | 27.75 | 9068.697600 | 7248 | 1 | 95
|
||||
| sb_0__1_ | 51.68 | 9809.408000 | 7840 | 1 | 138
|
||||
| sb_0__2_ | 31.95 | 9068.697600 | 7248 | 1 | 96
|
||||
| sb_1__0_ | 46.31 | 11471.001600 | 9168 | 1 | 150
|
||||
| sb_1__1_ | 66.68 | 12211.712000 | 9760 | 1 | 185
|
||||
| sb_1__2_ | 48.12 | 11471.001600 | 9168 | 1 | 140
|
||||
| sb_2__0_ | 40.31 | 9068.697600 | 7248 | 1 | 107
|
||||
| sb_2__1_ | 60.96 | 9809.408000 | 7840 | 1 | 151
|
||||
| sb_2__2_ | 41.16 | 9068.697600 | 7248 | 1 | 89
|
||||
| cbx_1__0_ | 54.01 | 5925.683200 | 4736 | 2 | 140
|
||||
| cbx_1__1_ | 74.16 | 5925.683200 | 4736 | 2 | 112
|
||||
| cbx_1__2_ | 76.12 | 5925.683200 | 4736 | 2 | 104
|
||||
| cby_0__1_ | 29.85 | 5184.972800 | 4144 | 2 | 106
|
||||
| cby_1__1_ | 79.92 | 5184.972800 | 4144 | 2 | 95
|
||||
| cby_2__1_ | 80.91 | 5184.972800 | 4144 | 2 | 87
|
||||
| grid_clb_1__1_ | 76.73 | 12071.577600 | 9648 | 4 | 52
|
||||
|
|
|
|||
|
|
|
@ -1,27 +1,31 @@
|
|||
Ref Name Total Area Utilization_% Instance Count
|
||||
------------------------------------------------------------------------------------
|
||||
sky130_fd_sc_hd__mux2_1 32250.931200 6.62 2864
|
||||
sky130_fd_sc_hd__dfxbp_1 19755.196800 4.06 831
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 4604.416000 0.95 368
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 4579.392000 0.94 366
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 3275.641600 0.67 374
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 2682.572800 0.55 268
|
||||
sky130_fd_sc_hd__buf_4 2169.580800 0.45 289
|
||||
sky130_fd_sc_hd__sdfxtp_1 1051.008000 0.22 40
|
||||
sky130_fd_sc_hd__buf_6 1035.993600 0.21 92
|
||||
sky130_fd_sc_hd__buf_2 410.393600 0.08 82
|
||||
sky130_fd_sc_hd__dlygate4sd1_1 385.369600 0.08 44
|
||||
sky130_fd_sc_hd__inv_1 360.345600 0.07 96
|
||||
sky130_fd_sc_hd__mux2_8 289.027200 0.06 11
|
||||
----------------------------------------------------------------------------------------------------
|
||||
sky130_fd_sc_hd__mux2_1 33410.793600 6.86 2967
|
||||
sky130_fd_sc_hd__dfxbp_1 31285.004800 6.43 1316
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 9258.880000 1.90 740
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 9071.200000 1.86 725
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 5695.462400 1.17 569
|
||||
sky130_fd_sc_hd__buf_4 2552.448000 0.52 340
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 1769.196800 0.36 202
|
||||
sky130_fd_sc_hd__sdfxtp_1 1681.612800 0.35 64
|
||||
sky130_fd_sc_hd__mux2_8 1208.659200 0.25 46
|
||||
sky130_fd_sc_hd__dlygate4sd1_1 613.088000 0.13 70
|
||||
sky130_fd_sc_hd__buf_2 375.360000 0.08 75
|
||||
sky130_fd_sc_hd__inv_1 375.360000 0.08 100
|
||||
sky130_fd_sc_hd__conb_1 326.563200 0.07 87
|
||||
sky130_fd_sc_hd__or2_0 200.192000 0.04 32
|
||||
sky130_fd_sc_hd__clkbuf_8 192.684800 0.04 14
|
||||
sky130_fd_sc_hd__conb_1 187.680000 0.04 50
|
||||
sky130_fd_sc_hd__clkinvlp_2 65.062400 0.01 13
|
||||
sky130_fd_sc_hd__bufinv_8 35.033600 0.01 2
|
||||
sky130_fd_sc_hd__bufinv_16 30.028800 0.01 1
|
||||
sky130_fd_sc_hd__buf_6 135.129600 0.03 12
|
||||
sky130_fd_sc_hd__buf_12 80.076800 0.02 4
|
||||
sky130_fd_sc_hd__buf_8 75.072000 0.02 5
|
||||
sky130_fd_sc_hd__clkbuf_1 60.057600 0.01 16
|
||||
sky130_fd_sc_hd__clkinv_16 30.028800 0.01 1
|
||||
sky130_fd_sc_hd__mux2_4 30.028800 0.01 2
|
||||
sky130_fd_sc_hd__clkbuf_1 7.507200 0.00 2
|
||||
FPGA_BBOX_AREA 189421.6704
|
||||
sky130_fd_sc_hd__clkdlybuf4s50_2 22.521600 0.00 2
|
||||
sky130_fd_sc_hd__clkinvlp_4 22.521600 0.00 3
|
||||
sky130_fd_sc_hd__clkinvlp_2 20.019200 0.00 4
|
||||
sky130_fd_sc_hd__clkinv_4 8.758400 0.00 1
|
||||
sky130_fd_sc_hd__inv_4 6.256000 0.00 1
|
||||
sky130_fd_sc_hd__clkinv_2 5.004800 0.00 1
|
||||
sky130_fd_sc_hd__inv_2 3.753600 0.00 1
|
||||
FPGA_BBOX_AREA 229900.4928
|
||||
CORE_BBOX_AREA 486866.944
|
||||
FPGA_BBOX_UTIL 38.90625
|
||||
FPGA_BBOX_UTIL 47.2203947368
|
||||
|
|
|
|||
|
Can't render this file because it has a wrong number of fields in line 2.
|
|
|
@ -6,7 +6,7 @@ Report : clock timing
|
|||
-setup
|
||||
Design : fpga_core
|
||||
Version: P-2019.03-SP4
|
||||
Date : Sat Nov 7 23:46:49 2020
|
||||
Date : Sun Nov 8 18:28:15 2020
|
||||
****************************************
|
||||
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
|
||||
|
||||
|
|
@ -16,7 +16,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
|
|||
--- Latency ---
|
||||
Clock Pin Trans Source Offset Network Total Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.080 0.000 -- 0.051 0.051 rp-+ nominal
|
||||
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.162 0.000 -- 0.429 0.429 rp-+ nominal
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
Mode: full_chip
|
||||
|
|
@ -25,7 +25,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
|
|||
--- Latency ---
|
||||
Clock Pin Trans Source Offset Network Total Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxbp_1_0_/CLK 2.855 0.000 -- 6.358 6.358 rp-+ nominal
|
||||
sb_0__2_/mem_right_track_0/sky130_fd_sc_hd__dfxbp_1_1_/CLK 0.347 0.000 -- 4.898 4.898 rp-+ nominal
|
||||
---------------------------------------------------------------------------------------------------
|
||||
****************************************
|
||||
Report : clock timing
|
||||
|
|
@ -34,7 +34,7 @@ Report : clock timing
|
|||
-setup
|
||||
Design : fpga_core
|
||||
Version: P-2019.03-SP4
|
||||
Date : Sat Nov 7 23:46:49 2020
|
||||
Date : Sun Nov 8 18:28:15 2020
|
||||
****************************************
|
||||
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
|
||||
|
||||
|
|
@ -43,8 +43,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
|
|||
|
||||
Clock Pin Latency CRP Skew Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.051 rp-+ nominal
|
||||
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.026 0.000 0.024 rp-+ nominal
|
||||
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.427 rp-+ nominal
|
||||
grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.026 0.000 0.401 rp-+ nominal
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
|
|
@ -53,8 +53,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
|
|||
|
||||
Clock Pin Latency CRP Skew Corner
|
||||
---------------------------------------------------------------------------------------------------
|
||||
grid_clb_1__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxbp_1_1_/CLK 5.290 rp-+ nominal
|
||||
cby_1__2_/mem_right_ipin_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.099 0.000 2.191 rp-+ nominal
|
||||
cby_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.374 rp-+ nominal
|
||||
sb_2__0_/mem_top_track_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 0.949 0.000 2.424 rp-+ nominal
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
|
||||
|
|
@ -63,7 +63,7 @@ Report : global timing
|
|||
-format { narrow }
|
||||
Design : fpga_core
|
||||
Version: P-2019.03-SP4
|
||||
Date : Sat Nov 7 23:46:49 2020
|
||||
Date : Sun Nov 8 18:28:15 2020
|
||||
****************************************
|
||||
|
||||
No setup violations found.
|
||||
|
|
@ -73,8 +73,8 @@ Hold violations
|
|||
--------------------------------------------------------------
|
||||
Total reg->reg in->reg reg->out in->out
|
||||
--------------------------------------------------------------
|
||||
WNS -2.785 -2.785 0.000 0.000 0.000
|
||||
TNS -3.014 -3.014 0.000 0.000 0.000
|
||||
WNS -1.248 -1.248 0.000 0.000 0.000
|
||||
TNS -1.390 -1.390 0.000 0.000 0.000
|
||||
NUM 2 2 0 0 0
|
||||
--------------------------------------------------------------
|
||||
|
||||
|
|
|
|||
BIN
FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds (Stored with Git LFS)
BIN
FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds (Stored with Git LFS)
Binary file not shown.
BIN
FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__1__icv_in_design.gds (Stored with Git LFS)
BIN
FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__1__icv_in_design.gds (Stored with Git LFS)
Binary file not shown.
BIN
FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__2__icv_in_design.gds (Stored with Git LFS)
BIN
FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__2__icv_in_design.gds (Stored with Git LFS)
Binary file not shown.
BIN
FPGA22_HIER_SKY_PNR/modules/gds/cby_0__1__icv_in_design.gds (Stored with Git LFS)
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FPGA22_HIER_SKY_PNR/modules/gds/cby_0__1__icv_in_design.gds (Stored with Git LFS)
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@ -4,7 +4,7 @@
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//
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//
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//
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module direct_interc ( in , out ) ;
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module cby_0__1__direct_interc ( in , out ) ;
|
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input [0:0] in ;
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output [0:0] out ;
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||||
|
|
@ -12,8 +12,8 @@ assign out[0] = in[0] ;
|
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endmodule
|
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|
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|
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module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head ,
|
||||
ccff_tail , mem_out , mem_outb ) ;
|
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module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk ,
|
||||
ccff_head , ccff_tail , mem_out , mem_outb ) ;
|
||||
input [0:0] prog_clk ;
|
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input [0:0] ccff_head ;
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output [0:0] ccff_tail ;
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@ -22,13 +22,15 @@ output [0:0] mem_outb ;
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|
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sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) ,
|
||||
.CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ;
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sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) ,
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sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) ,
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.X ( net_net_89 ) ) ;
|
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sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) ,
|
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.X ( ccff_tail[0] ) ) ;
|
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endmodule
|
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|
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module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT ,
|
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FPGA_DIR , p_abuf0 , p_abuf1 ) ;
|
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module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
|
||||
FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ;
|
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input SOC_IN ;
|
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output SOC_OUT ;
|
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output SOC_DIR ;
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@ -42,17 +44,17 @@ wire aps_rename_2_ ;
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|||
|
||||
assign SOC_OUT = FPGA_OUT ;
|
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|
||||
sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ;
|
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sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) ,
|
||||
.X ( aps_rename_2_ ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) ,
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) ,
|
||||
.X ( SOC_DIR ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module logical_tile_io_mode_physical__iopad ( prog_clk ,
|
||||
module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad ,
|
||||
ccff_tail , p_abuf0 , p_abuf1 ) ;
|
||||
|
|
@ -69,22 +71,24 @@ output p_abuf1 ;
|
|||
|
||||
wire [0:0] EMBEDDED_IO_0_en ;
|
||||
|
||||
EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) ,
|
||||
cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ (
|
||||
.SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) ,
|
||||
.SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) ,
|
||||
.SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ,
|
||||
.FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
|
||||
.FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ,
|
||||
.p_abuf1 ( p_abuf1 ) ) ;
|
||||
EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem (
|
||||
cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem (
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ,
|
||||
.mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR ,
|
||||
io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ;
|
||||
module cby_0__1__logical_tile_io_mode_io_ ( prog_clk ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad ,
|
||||
ccff_tail , p_abuf0 ) ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
|
||||
|
|
@ -95,7 +99,7 @@ output [0:0] io_inpad ;
|
|||
output [0:0] ccff_tail ;
|
||||
output p_abuf0 ;
|
||||
|
||||
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
||||
cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) ,
|
||||
|
|
@ -103,17 +107,17 @@ logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
|||
.iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
|
||||
.iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ,
|
||||
.p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ;
|
||||
direct_interc direct_interc_0_ (
|
||||
cby_0__1__direct_interc direct_interc_0_ (
|
||||
.in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
|
||||
.out ( { p_abuf1 } ) ) ;
|
||||
direct_interc direct_interc_1_ (
|
||||
cby_0__1__direct_interc direct_interc_1_ (
|
||||
.in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
|
||||
.out ( io_outpad ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail ,
|
||||
mem_out , mem_outb ) ;
|
||||
module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
|
||||
ccff_tail , mem_out , mem_outb ) ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] ccff_tail ;
|
||||
|
|
@ -133,12 +137,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) ,
|
|||
endmodule
|
||||
|
||||
|
||||
module const1 ( const1 ) ;
|
||||
module cby_0__1__const1 ( const1 ) ;
|
||||
output [0:0] const1 ;
|
||||
endmodule
|
||||
|
||||
|
||||
module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
|
||||
module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
|
||||
input [0:9] in ;
|
||||
input [0:3] sram ;
|
||||
input [0:3] sram_inv ;
|
||||
|
|
@ -156,10 +160,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
|
|||
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
|
||||
|
||||
const1 const1_0_ (
|
||||
cby_0__1__const1 const1_0_ (
|
||||
.const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
|
||||
.A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
|
||||
|
|
@ -189,6 +191,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
|
|||
.A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 (
|
||||
.A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -197,7 +201,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head ,
|
|||
gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ ,
|
||||
right_width_0_height_0__pin_1_upper ,
|
||||
right_width_0_height_0__pin_1_lower ) ;
|
||||
right_width_0_height_0__pin_1_lower , prog_clk__FEEDTHRU_1 ) ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:19] chany_bottom_in ;
|
||||
input [0:19] chany_top_in ;
|
||||
|
|
@ -212,246 +216,243 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
|
|||
input [0:0] right_width_0_height_0__pin_0_ ;
|
||||
output [0:0] right_width_0_height_0__pin_1_upper ;
|
||||
output [0:0] right_width_0_height_0__pin_1_lower ;
|
||||
output [0:0] prog_clk__FEEDTHRU_1 ;
|
||||
|
||||
wire ropt_net_162 ;
|
||||
wire ropt_net_166 ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ;
|
||||
//
|
||||
|
||||
mux_tree_tapbuf_size10 mux_right_ipin_0 (
|
||||
cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
|
||||
.in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] ,
|
||||
chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] ,
|
||||
chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] ,
|
||||
chany_top_in[16] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
|
||||
.sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) ,
|
||||
.out ( left_grid_pin_0_ ) , .p0 ( optlc_net_157 ) ) ;
|
||||
mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( ccff_head ) ,
|
||||
.sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) ,
|
||||
.out ( { ropt_net_160 } ) ,
|
||||
.p0 ( optlc_net_155 ) ) ;
|
||||
cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 (
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( { ccff_tail_mid } ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ,
|
||||
.mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ;
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) ,
|
||||
cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) ,
|
||||
.io_outpad ( right_width_0_height_0__pin_0_ ) ,
|
||||
.ccff_head ( { ccff_tail_mid } ) ,
|
||||
.io_inpad ( { aps_rename_4_ } ) ,
|
||||
.ccff_tail ( { ropt_net_163 } ) ,
|
||||
.p_abuf0 ( ropt_net_162 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) ,
|
||||
.HI ( optlc_net_157 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 (
|
||||
.A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) ,
|
||||
.X ( ropt_net_229 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) ,
|
||||
.X ( ropt_net_227 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) ,
|
||||
.X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) ,
|
||||
.X ( ropt_net_210 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) ,
|
||||
.X ( ccff_tail[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) ,
|
||||
.X ( chany_bottom_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) ,
|
||||
.X ( ropt_net_228 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) ,
|
||||
.X ( ropt_net_222 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) ,
|
||||
.X ( chany_bottom_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 (
|
||||
.A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) ,
|
||||
.X ( chany_bottom_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) ,
|
||||
.X ( ropt_net_202 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) ,
|
||||
.X ( chany_bottom_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) ,
|
||||
.X ( ropt_net_218 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) ,
|
||||
.X ( ropt_net_208 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) ,
|
||||
.X ( ropt_net_209 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) ,
|
||||
.X ( ropt_net_212 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) ,
|
||||
.X ( ropt_net_203 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) ,
|
||||
.X ( ropt_net_214 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) ,
|
||||
.X ( ropt_net_217 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) ,
|
||||
.X ( chany_bottom_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) ,
|
||||
.X ( ropt_net_204 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) ,
|
||||
.X ( ropt_net_175 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) ,
|
||||
.X ( ropt_net_213 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) ,
|
||||
.X ( ropt_net_220 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) ,
|
||||
.X ( ropt_net_221 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) ,
|
||||
.X ( ropt_net_216 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) ,
|
||||
.X ( ropt_net_219 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) ,
|
||||
.X ( chany_bottom_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) ,
|
||||
.X ( ropt_net_201 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) ,
|
||||
.X ( ropt_net_206 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) ,
|
||||
.X ( ropt_net_226 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) ,
|
||||
.X ( ropt_net_223 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) ,
|
||||
.X ( ropt_net_200 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) ,
|
||||
.X ( ropt_net_177 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) ,
|
||||
.X ( ropt_net_225 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) ,
|
||||
.X ( ropt_net_205 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) ,
|
||||
.X ( ropt_net_215 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) ,
|
||||
.X ( ropt_net_199 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) ,
|
||||
.X ( ropt_net_224 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) ,
|
||||
.X ( chany_bottom_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) ,
|
||||
.X ( ropt_net_211 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) ,
|
||||
.X ( chany_top_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) ,
|
||||
.X ( chany_bottom_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) ,
|
||||
.X ( chany_bottom_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) ,
|
||||
.X ( chany_bottom_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) ,
|
||||
.X ( chany_bottom_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) ,
|
||||
.X ( chany_bottom_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) ,
|
||||
.X ( chany_top_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) ,
|
||||
.X ( ropt_net_174 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) ,
|
||||
.X ( chany_top_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) ,
|
||||
.X ( chany_top_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) ,
|
||||
.X ( chany_bottom_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) ,
|
||||
.X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) ,
|
||||
.X ( ropt_net_182 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) ,
|
||||
.X ( chany_top_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) ,
|
||||
.X ( BUF_net_64 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) ,
|
||||
.X ( chany_top_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) ,
|
||||
.X ( chany_top_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) ,
|
||||
.X ( ropt_net_187 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) ,
|
||||
.X ( chany_top_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) ,
|
||||
.X ( ropt_net_173 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) ,
|
||||
.X ( BUF_net_72 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) ,
|
||||
.X ( chany_bottom_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) ,
|
||||
.X ( chany_top_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) ,
|
||||
.X ( chany_top_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) ,
|
||||
.X ( ropt_net_189 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) ,
|
||||
.X ( chany_bottom_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) ,
|
||||
.X ( chany_top_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) ,
|
||||
.X ( chany_bottom_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) ,
|
||||
.X ( chany_top_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) ,
|
||||
.X ( chany_bottom_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) ,
|
||||
.X ( chany_top_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) ,
|
||||
.X ( right_width_0_height_0__pin_1_lower[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) ,
|
||||
.io_inpad ( { aps_rename_13_ } ) ,
|
||||
.ccff_tail ( { ropt_net_195 } ) ,
|
||||
.p_abuf0 ( ropt_net_166 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) ,
|
||||
.HI ( optlc_net_155 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) ,
|
||||
.X ( chany_top_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) ,
|
||||
sky130_fd_sc_hd__buf_2 prog_clk_0__bip423 ( .A ( prog_clk[0] ) ,
|
||||
.X ( ctsbuf_net_1156 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) ,
|
||||
.X ( chany_bottom_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) ,
|
||||
.X ( prog_clk__FEEDTHRU_1[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) ,
|
||||
.X ( chany_top_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) ,
|
||||
.X ( chany_top_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) ,
|
||||
.X ( chany_bottom_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) ,
|
||||
.X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) ,
|
||||
.X ( left_grid_pin_0_[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) ,
|
||||
.X ( chany_top_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) ,
|
||||
.X ( ropt_net_171 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) ,
|
||||
.X ( chany_top_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) ,
|
||||
.X ( ropt_net_180 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) ,
|
||||
.X ( ropt_net_160 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) ,
|
||||
.X ( ropt_net_194 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) ,
|
||||
.X ( ropt_net_190 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) ,
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) ,
|
||||
.X ( ropt_net_222 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) ,
|
||||
.X ( ropt_net_211 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) ,
|
||||
.X ( ropt_net_215 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) ,
|
||||
.X ( chany_bottom_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) ,
|
||||
.X ( ropt_net_195 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) ,
|
||||
.X ( ropt_net_186 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) ,
|
||||
.X ( ropt_net_191 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) ,
|
||||
.X ( ropt_net_165 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) ,
|
||||
.X ( ropt_net_183 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) ,
|
||||
.X ( ropt_net_176 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) ,
|
||||
.X ( ropt_net_185 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) ,
|
||||
.X ( ropt_net_193 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) ,
|
||||
.X ( ropt_net_179 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) ,
|
||||
.X ( ropt_net_184 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) ,
|
||||
.X ( ropt_net_181 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) ,
|
||||
.X ( ropt_net_192 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) ,
|
||||
.X ( ropt_net_188 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) ,
|
||||
.X ( chany_bottom_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) ,
|
||||
.X ( ropt_net_196 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) ,
|
||||
.X ( ropt_net_178 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) ,
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) ,
|
||||
.X ( ropt_net_230 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) ,
|
||||
.X ( ropt_net_204 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) ,
|
||||
.X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) ,
|
||||
.X ( ropt_net_231 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) ,
|
||||
.X ( ropt_net_228 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) ,
|
||||
.X ( ropt_net_220 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) ,
|
||||
.X ( chany_bottom_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 (
|
||||
.A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) ,
|
||||
.X ( right_width_0_height_0__pin_1_lower[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) ,
|
||||
.X ( ropt_net_225 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) ,
|
||||
.X ( chany_top_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) ,
|
||||
.X ( chany_bottom_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) ,
|
||||
.X ( chany_bottom_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) ,
|
||||
.X ( chany_bottom_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) ,
|
||||
.X ( ropt_net_203 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) ,
|
||||
.X ( ropt_net_207 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) ,
|
||||
.X ( ropt_net_226 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) ,
|
||||
.X ( chany_bottom_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) ,
|
||||
.X ( chany_bottom_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) ,
|
||||
.X ( ropt_net_200 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) ,
|
||||
.X ( ropt_net_206 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) ,
|
||||
.X ( ropt_net_202 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) ,
|
||||
.X ( chany_bottom_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) ,
|
||||
.X ( ropt_net_205 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) ,
|
||||
.X ( ropt_net_209 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) ,
|
||||
.X ( ropt_net_213 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) ,
|
||||
.X ( BUF_net_49 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) ,
|
||||
.X ( ropt_net_196 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 (
|
||||
.A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) ,
|
||||
.X ( ropt_net_214 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) ,
|
||||
.X ( BUF_net_53 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) ,
|
||||
.X ( ropt_net_180 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) ,
|
||||
.X ( BUF_net_55 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) ,
|
||||
.X ( ropt_net_182 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 (
|
||||
.A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) ,
|
||||
.X ( ropt_net_185 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) ,
|
||||
.X ( ropt_net_190 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) ,
|
||||
.X ( ropt_net_187 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) ,
|
||||
.X ( chany_top_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) ,
|
||||
.X ( ropt_net_227 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) ,
|
||||
.X ( chany_bottom_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) ,
|
||||
.X ( ropt_net_201 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) ,
|
||||
.X ( chany_bottom_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) ,
|
||||
.X ( ropt_net_218 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) ,
|
||||
.X ( ropt_net_177 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) ,
|
||||
.X ( ropt_net_191 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) ,
|
||||
.X ( chany_top_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) ,
|
||||
.X ( ropt_net_158 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) ,
|
||||
.X ( ropt_net_163 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) ,
|
||||
.X ( chany_top_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) ,
|
||||
.X ( chany_bottom_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) ,
|
||||
.X ( chany_top_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) ,
|
||||
.X ( ropt_net_224 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) ,
|
||||
.X ( ropt_net_217 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) ,
|
||||
.X ( ropt_net_181 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) ,
|
||||
.X ( ropt_net_157 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) ,
|
||||
.X ( ropt_net_192 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) ,
|
||||
.X ( chany_bottom_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) ,
|
||||
.X ( ropt_net_208 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) ,
|
||||
.X ( ropt_net_165 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) ,
|
||||
.X ( chany_top_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) ,
|
||||
.X ( ccff_tail[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) ,
|
||||
.X ( ropt_net_223 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) ,
|
||||
.X ( ropt_net_221 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) ,
|
||||
.X ( chany_top_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) ,
|
||||
.X ( chany_top_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) ,
|
||||
.X ( chany_bottom_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) ,
|
||||
.X ( chany_top_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) ,
|
||||
.X ( chany_bottom_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) ,
|
||||
.X ( chany_bottom_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) ,
|
||||
.X ( ropt_net_169 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) ,
|
||||
.X ( chany_top_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) ,
|
||||
.X ( chany_bottom_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) ,
|
||||
.X ( chany_top_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) ,
|
||||
.X ( chany_top_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) ,
|
||||
.X ( chany_bottom_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) ,
|
||||
.X ( chany_bottom_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) ,
|
||||
.X ( ropt_net_219 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) ,
|
||||
.X ( ropt_net_216 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) ,
|
||||
.X ( ropt_net_194 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) ,
|
||||
.X ( ropt_net_197 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) ,
|
||||
.X ( ropt_net_193 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) ,
|
||||
.X ( ropt_net_161 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) ,
|
||||
.X ( ropt_net_172 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -4,7 +4,7 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
module direct_interc ( in , out ) ;
|
||||
module cby_0__1__direct_interc ( in , out ) ;
|
||||
input [0:0] in ;
|
||||
output [0:0] out ;
|
||||
|
||||
|
|
@ -12,8 +12,8 @@ assign out[0] = in[0] ;
|
|||
endmodule
|
||||
|
||||
|
||||
module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head ,
|
||||
ccff_tail , mem_out , mem_outb ) ;
|
||||
module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk ,
|
||||
ccff_head , ccff_tail , mem_out , mem_outb ) ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] ccff_tail ;
|
||||
|
|
@ -22,13 +22,15 @@ output [0:0] mem_outb ;
|
|||
|
||||
sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) ,
|
||||
.CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) ,
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) ,
|
||||
.X ( net_net_89 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) ,
|
||||
.X ( ccff_tail[0] ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT ,
|
||||
FPGA_DIR , p_abuf0 , p_abuf1 ) ;
|
||||
module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
|
||||
FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ;
|
||||
input SOC_IN ;
|
||||
output SOC_OUT ;
|
||||
output SOC_DIR ;
|
||||
|
|
@ -42,17 +44,17 @@ wire aps_rename_2_ ;
|
|||
|
||||
assign SOC_OUT = FPGA_OUT ;
|
||||
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) ,
|
||||
.X ( aps_rename_2_ ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) ,
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) ,
|
||||
.X ( SOC_DIR ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module logical_tile_io_mode_physical__iopad ( prog_clk ,
|
||||
module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad ,
|
||||
ccff_tail , p_abuf0 , p_abuf1 ) ;
|
||||
|
|
@ -69,22 +71,24 @@ output p_abuf1 ;
|
|||
|
||||
wire [0:0] EMBEDDED_IO_0_en ;
|
||||
|
||||
EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) ,
|
||||
cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ (
|
||||
.SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) ,
|
||||
.SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) ,
|
||||
.SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ,
|
||||
.FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
|
||||
.FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ,
|
||||
.p_abuf1 ( p_abuf1 ) ) ;
|
||||
EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem (
|
||||
cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem (
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ,
|
||||
.mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR ,
|
||||
io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ;
|
||||
module cby_0__1__logical_tile_io_mode_io_ ( prog_clk ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad ,
|
||||
ccff_tail , p_abuf0 ) ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ;
|
||||
|
|
@ -95,7 +99,7 @@ output [0:0] io_inpad ;
|
|||
output [0:0] ccff_tail ;
|
||||
output p_abuf0 ;
|
||||
|
||||
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
||||
cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) ,
|
||||
|
|
@ -103,17 +107,17 @@ logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
|||
.iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
|
||||
.iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ,
|
||||
.p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ;
|
||||
direct_interc direct_interc_0_ (
|
||||
cby_0__1__direct_interc direct_interc_0_ (
|
||||
.in ( { SYNOPSYS_UNCONNECTED_1 } ) ,
|
||||
.out ( { p_abuf1 } ) ) ;
|
||||
direct_interc direct_interc_1_ (
|
||||
cby_0__1__direct_interc direct_interc_1_ (
|
||||
.in ( { SYNOPSYS_UNCONNECTED_2 } ) ,
|
||||
.out ( io_outpad ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail ,
|
||||
mem_out , mem_outb ) ;
|
||||
module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head ,
|
||||
ccff_tail , mem_out , mem_outb ) ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] ccff_tail ;
|
||||
|
|
@ -133,7 +137,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) ,
|
|||
endmodule
|
||||
|
||||
|
||||
module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
|
||||
module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
|
||||
input [0:9] in ;
|
||||
input [0:3] sram ;
|
||||
input [0:3] sram_inv ;
|
||||
|
|
@ -151,8 +155,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
|
|||
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
|
||||
|
||||
sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ (
|
||||
.A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
|
||||
|
|
@ -182,6 +184,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
|
|||
.A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 (
|
||||
.A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -190,7 +194,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head ,
|
|||
gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT ,
|
||||
gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ ,
|
||||
right_width_0_height_0__pin_1_upper ,
|
||||
right_width_0_height_0__pin_1_lower ) ;
|
||||
right_width_0_height_0__pin_1_lower , prog_clk__FEEDTHRU_1 ) ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:19] chany_bottom_in ;
|
||||
input [0:19] chany_top_in ;
|
||||
|
|
@ -205,246 +209,243 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ;
|
|||
input [0:0] right_width_0_height_0__pin_0_ ;
|
||||
output [0:0] right_width_0_height_0__pin_1_upper ;
|
||||
output [0:0] right_width_0_height_0__pin_1_lower ;
|
||||
output [0:0] prog_clk__FEEDTHRU_1 ;
|
||||
|
||||
wire ropt_net_162 ;
|
||||
wire ropt_net_166 ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ;
|
||||
//
|
||||
|
||||
mux_tree_tapbuf_size10 mux_right_ipin_0 (
|
||||
cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
|
||||
.in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] ,
|
||||
chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] ,
|
||||
chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] ,
|
||||
chany_top_in[16] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
|
||||
.sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) ,
|
||||
.out ( left_grid_pin_0_ ) , .p0 ( optlc_net_157 ) ) ;
|
||||
mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( ccff_head ) ,
|
||||
.sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) ,
|
||||
.out ( { ropt_net_160 } ) ,
|
||||
.p0 ( optlc_net_155 ) ) ;
|
||||
cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 (
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( { ccff_tail_mid } ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ,
|
||||
.mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ;
|
||||
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) ,
|
||||
cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) ,
|
||||
.io_outpad ( right_width_0_height_0__pin_0_ ) ,
|
||||
.ccff_head ( { ccff_tail_mid } ) ,
|
||||
.io_inpad ( { aps_rename_4_ } ) ,
|
||||
.ccff_tail ( { ropt_net_163 } ) ,
|
||||
.p_abuf0 ( ropt_net_162 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) ,
|
||||
.HI ( optlc_net_157 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 (
|
||||
.A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) ,
|
||||
.X ( ropt_net_229 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) ,
|
||||
.X ( ropt_net_227 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) ,
|
||||
.X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) ,
|
||||
.X ( ropt_net_210 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) ,
|
||||
.X ( ccff_tail[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) ,
|
||||
.X ( chany_bottom_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) ,
|
||||
.X ( ropt_net_228 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) ,
|
||||
.X ( ropt_net_222 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) ,
|
||||
.X ( chany_bottom_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 (
|
||||
.A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) ,
|
||||
.X ( chany_bottom_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) ,
|
||||
.X ( ropt_net_202 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) ,
|
||||
.X ( chany_bottom_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) ,
|
||||
.X ( ropt_net_218 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) ,
|
||||
.X ( ropt_net_208 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) ,
|
||||
.X ( ropt_net_209 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) ,
|
||||
.X ( ropt_net_212 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) ,
|
||||
.X ( ropt_net_203 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) ,
|
||||
.X ( ropt_net_214 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) ,
|
||||
.X ( ropt_net_217 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) ,
|
||||
.X ( chany_bottom_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) ,
|
||||
.X ( ropt_net_204 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) ,
|
||||
.X ( ropt_net_175 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) ,
|
||||
.X ( ropt_net_213 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) ,
|
||||
.X ( ropt_net_220 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) ,
|
||||
.X ( ropt_net_221 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) ,
|
||||
.X ( ropt_net_216 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) ,
|
||||
.X ( ropt_net_219 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) ,
|
||||
.X ( chany_bottom_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) ,
|
||||
.X ( ropt_net_201 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) ,
|
||||
.X ( ropt_net_206 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) ,
|
||||
.X ( ropt_net_226 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) ,
|
||||
.X ( ropt_net_223 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) ,
|
||||
.X ( ropt_net_200 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) ,
|
||||
.X ( ropt_net_177 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) ,
|
||||
.X ( ropt_net_225 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) ,
|
||||
.X ( ropt_net_205 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) ,
|
||||
.X ( ropt_net_215 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) ,
|
||||
.X ( ropt_net_199 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) ,
|
||||
.X ( ropt_net_224 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) ,
|
||||
.X ( chany_bottom_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) ,
|
||||
.X ( ropt_net_211 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) ,
|
||||
.X ( chany_top_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) ,
|
||||
.X ( chany_bottom_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) ,
|
||||
.X ( chany_bottom_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) ,
|
||||
.X ( chany_bottom_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) ,
|
||||
.X ( chany_bottom_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) ,
|
||||
.X ( chany_bottom_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) ,
|
||||
.X ( chany_top_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) ,
|
||||
.X ( ropt_net_174 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) ,
|
||||
.X ( chany_top_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) ,
|
||||
.X ( chany_top_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) ,
|
||||
.X ( chany_bottom_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) ,
|
||||
.X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) ,
|
||||
.X ( ropt_net_182 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) ,
|
||||
.X ( chany_top_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) ,
|
||||
.X ( BUF_net_64 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) ,
|
||||
.X ( chany_top_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) ,
|
||||
.X ( chany_top_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) ,
|
||||
.X ( ropt_net_187 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) ,
|
||||
.X ( chany_top_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) ,
|
||||
.X ( ropt_net_173 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) ,
|
||||
.X ( BUF_net_72 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) ,
|
||||
.X ( chany_bottom_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) ,
|
||||
.X ( chany_top_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) ,
|
||||
.X ( chany_top_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) ,
|
||||
.X ( ropt_net_189 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) ,
|
||||
.X ( chany_bottom_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) ,
|
||||
.X ( chany_top_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) ,
|
||||
.X ( chany_bottom_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) ,
|
||||
.X ( chany_top_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) ,
|
||||
.X ( chany_bottom_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) ,
|
||||
.X ( chany_top_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) ,
|
||||
.X ( right_width_0_height_0__pin_1_lower[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) ,
|
||||
.io_inpad ( { aps_rename_13_ } ) ,
|
||||
.ccff_tail ( { ropt_net_195 } ) ,
|
||||
.p_abuf0 ( ropt_net_166 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) ,
|
||||
.HI ( optlc_net_155 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) ,
|
||||
.X ( chany_top_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) ,
|
||||
sky130_fd_sc_hd__buf_2 prog_clk_0__bip423 ( .A ( prog_clk[0] ) ,
|
||||
.X ( ctsbuf_net_1156 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) ,
|
||||
.X ( chany_bottom_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) ,
|
||||
.X ( prog_clk__FEEDTHRU_1[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) ,
|
||||
.X ( chany_top_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) ,
|
||||
.X ( chany_top_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) ,
|
||||
.X ( chany_bottom_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) ,
|
||||
.X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) ,
|
||||
.X ( left_grid_pin_0_[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) ,
|
||||
.X ( chany_top_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) ,
|
||||
.X ( ropt_net_171 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) ,
|
||||
.X ( chany_top_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) ,
|
||||
.X ( ropt_net_180 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) ,
|
||||
.X ( ropt_net_160 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) ,
|
||||
.X ( ropt_net_194 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) ,
|
||||
.X ( ropt_net_190 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) ,
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) ,
|
||||
.X ( ropt_net_222 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) ,
|
||||
.X ( ropt_net_211 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) ,
|
||||
.X ( ropt_net_215 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) ,
|
||||
.X ( chany_bottom_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) ,
|
||||
.X ( ropt_net_195 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) ,
|
||||
.X ( ropt_net_186 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) ,
|
||||
.X ( ropt_net_191 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) ,
|
||||
.X ( ropt_net_165 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) ,
|
||||
.X ( ropt_net_183 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) ,
|
||||
.X ( ropt_net_176 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) ,
|
||||
.X ( ropt_net_185 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) ,
|
||||
.X ( ropt_net_193 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) ,
|
||||
.X ( ropt_net_179 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) ,
|
||||
.X ( ropt_net_184 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) ,
|
||||
.X ( ropt_net_181 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) ,
|
||||
.X ( ropt_net_192 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) ,
|
||||
.X ( ropt_net_188 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) ,
|
||||
.X ( chany_bottom_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) ,
|
||||
.X ( ropt_net_196 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) ,
|
||||
.X ( ropt_net_178 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) ,
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) ,
|
||||
.X ( ropt_net_230 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) ,
|
||||
.X ( ropt_net_204 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) ,
|
||||
.X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) ,
|
||||
.X ( ropt_net_231 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) ,
|
||||
.X ( ropt_net_228 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) ,
|
||||
.X ( ropt_net_220 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) ,
|
||||
.X ( chany_bottom_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 (
|
||||
.A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) ,
|
||||
.X ( right_width_0_height_0__pin_1_lower[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) ,
|
||||
.X ( ropt_net_225 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) ,
|
||||
.X ( chany_top_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) ,
|
||||
.X ( chany_bottom_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) ,
|
||||
.X ( chany_bottom_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) ,
|
||||
.X ( chany_bottom_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) ,
|
||||
.X ( ropt_net_203 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) ,
|
||||
.X ( ropt_net_207 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) ,
|
||||
.X ( ropt_net_226 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) ,
|
||||
.X ( chany_bottom_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) ,
|
||||
.X ( chany_bottom_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) ,
|
||||
.X ( ropt_net_200 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) ,
|
||||
.X ( ropt_net_206 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) ,
|
||||
.X ( ropt_net_202 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) ,
|
||||
.X ( chany_bottom_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) ,
|
||||
.X ( ropt_net_205 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) ,
|
||||
.X ( ropt_net_209 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) ,
|
||||
.X ( ropt_net_213 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) ,
|
||||
.X ( BUF_net_49 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) ,
|
||||
.X ( ropt_net_196 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 (
|
||||
.A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) ,
|
||||
.X ( ropt_net_214 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) ,
|
||||
.X ( BUF_net_53 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) ,
|
||||
.X ( ropt_net_180 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) ,
|
||||
.X ( BUF_net_55 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) ,
|
||||
.X ( ropt_net_182 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 (
|
||||
.A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) ,
|
||||
.X ( ropt_net_185 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) ,
|
||||
.X ( ropt_net_190 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) ,
|
||||
.X ( ropt_net_187 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) ,
|
||||
.X ( chany_top_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) ,
|
||||
.X ( ropt_net_227 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) ,
|
||||
.X ( chany_bottom_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) ,
|
||||
.X ( ropt_net_201 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) ,
|
||||
.X ( chany_bottom_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) ,
|
||||
.X ( ropt_net_218 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) ,
|
||||
.X ( ropt_net_177 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) ,
|
||||
.X ( ropt_net_191 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) ,
|
||||
.X ( chany_top_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) ,
|
||||
.X ( ropt_net_158 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) ,
|
||||
.X ( ropt_net_163 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) ,
|
||||
.X ( chany_top_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) ,
|
||||
.X ( chany_bottom_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) ,
|
||||
.X ( chany_top_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) ,
|
||||
.X ( ropt_net_224 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) ,
|
||||
.X ( ropt_net_217 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) ,
|
||||
.X ( ropt_net_181 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) ,
|
||||
.X ( ropt_net_157 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) ,
|
||||
.X ( ropt_net_192 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) ,
|
||||
.X ( chany_bottom_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) ,
|
||||
.X ( ropt_net_208 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) ,
|
||||
.X ( ropt_net_165 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) ,
|
||||
.X ( chany_top_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) ,
|
||||
.X ( ccff_tail[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) ,
|
||||
.X ( ropt_net_223 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) ,
|
||||
.X ( ropt_net_221 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) ,
|
||||
.X ( chany_top_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) ,
|
||||
.X ( chany_top_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) ,
|
||||
.X ( chany_bottom_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) ,
|
||||
.X ( chany_top_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) ,
|
||||
.X ( chany_bottom_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) ,
|
||||
.X ( chany_bottom_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) ,
|
||||
.X ( ropt_net_169 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) ,
|
||||
.X ( chany_top_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) ,
|
||||
.X ( chany_bottom_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) ,
|
||||
.X ( chany_top_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) ,
|
||||
.X ( chany_top_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) ,
|
||||
.X ( chany_bottom_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) ,
|
||||
.X ( chany_bottom_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) ,
|
||||
.X ( ropt_net_219 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) ,
|
||||
.X ( ropt_net_216 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) ,
|
||||
.X ( ropt_net_194 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) ,
|
||||
.X ( ropt_net_197 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) ,
|
||||
.X ( ropt_net_193 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) ,
|
||||
.X ( ropt_net_161 ) ) ;
|
||||
sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) ,
|
||||
.X ( ropt_net_172 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
|
|||
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Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue