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Merge pull request #14 from LNIS-Projects/ganesh_dev 

Ganesh dev
This commit is contained in:
tangxifan 2020-11-09 09:04:27 -07:00 committed by GitHub
parent dbe8c73bdb 015c67e10f
commit 69afafb581
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137 changed files with 126813 additions and 112390 deletions
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47
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info
View File

@ -1,43 +1,48 @@
commit 48b2bff0d909e2c6d0740d2a5386123eb238349f
commit 55f7a2c187139d471143f91dc368bb1497e2eb78
Merge: 1f3e656f 93e7107d
Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com>
Date: Wed Nov 4 21:55:37 2020 -0700
Merge pull request #116 from LNIS-Projects/dev
Extended I/O Support for SoC I/O interface
commit 93e7107d800259ad9031c6b5d4572e8a971c6403
Author: tangxifan <tangxifan@gmail.com>
Date: Sun Sep 27 20:08:11 2020 -0600
Date: Wed Nov 4 20:59:34 2020 -0700
[OpenFPGA Tool] Update fabric key data structure to support regions
[Test] Add new test to CI
commit bbdea4a46b7aadd8a6f0fc45abdd39d1cc6d3057
commit bce8233019cec3b7f778befd9457c9c637b05c6c
Author: tangxifan <tangxifan@gmail.com>
Date: Sun Sep 27 19:23:13 2020 -0600
Date: Wed Nov 4 20:58:58 2020 -0700
[Regression Test] Remove out-of-update sub modules
[Arch] Bug fix in caravel arch
commit e95eacfbd9ec5e8d9aecab7572d4bad5265d9590
Merge: 32c43ffb 94047037
commit 6b48ee7f0bd6c86181cdbbb468c4cf8e7af5c4c6
Author: tangxifan <tangxifan@gmail.com>
Date: Sun Sep 27 17:01:57 2020 -0600
Date: Wed Nov 4 20:58:40 2020 -0700
Merge branch 'dev' into ganesh_dev
[Test] Add new test for caravel io support
commit 94047037c570b6a432fea8f363a5147df9bc918d
commit c85edb4738a24c394b5eeefb08586da7bd4ead6a
Author: tangxifan <tangxifan@gmail.com>
Date: Sun Sep 27 14:33:14 2020 -0600
Date: Wed Nov 4 20:52:47 2020 -0700
[OpenFPGA Tool] Streamline codes in openfpga arch parser
commit 94a1324f0527276546c3b2571b1a1b7700a473f7
Author: tangxifan <tangxifan@gmail.com>
Date: Sat Sep 26 14:31:57 2020 -0600
[Documentation] Remove deprecated XML syntax
On branch dev
Your branch is up to date with 'origin/dev'.
[Arch] Bug fix for embedded io arch
On branch master
Your branch is up to date with 'origin/master'.
Untracked files:
(use "git add <file>..." to include in what will be committed)
openfpga/openfpga
openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task
openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task
openfpga_flow/tasks/FPGA128128_FLAT_task
openfpga_flow/tasks/FPGA1616_FLAT_task
openfpga_flow/tasks/FPGA22_FLAT_task
openfpga_flow/tasks/FPGA22_FRAME_task
openfpga_flow/tasks/FPGA22_HIER_SKY_SC_MS_task
openfpga_flow/tasks/FPGA22_HIER_SKY_task
openfpga_flow/tasks/FPGA22_HIER_task
openfpga_flow/tasks/FPGA22_MB_task

37
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v
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@ -1,18 +1,17 @@
module fpga_core
(
input [0:0] prog_clk,
input [0:0] Test_en,
input [0:0] clk,
input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN,
output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT,
output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR,
input [0:0] ccff_head,
output [0:0] ccff_tail,
input sc_head,
output sc_tail
);
( prog_clk, Test_en, clk, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, ccff_head, ccff_tail, sc_head, sc_tail );
input [0:0] prog_clk;
input [0:0] Test_en;
input [0:0] clk;
input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN;
output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT;
output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR;
input [0:0] ccff_head;
output [0:0] ccff_tail;
input sc_head;
output sc_tail;
wire [0:0] cbx_1__0__0_bottom_grid_pin_0_;
wire [0:0] cbx_1__0__0_bottom_grid_pin_10_;
@ -425,8 +424,6 @@ module fpga_core
wire [0:19] sb_2__2__0_chanx_left_out;
wire [0:19] sb_2__2__0_chany_bottom_out;
wire [1:0] UNCONN;
wire [2:0] sc_out_wires;
wire [2:0] sc_in_wires;
wire [12:0] scff_Wires;
grid_clb
@ -434,7 +431,6 @@ module fpga_core
(
.SC_OUT_BOT(scff_Wires[5]),
.SC_IN_TOP(scff_Wires[3]),
.top_width_0_height_0__pin_33_(sc_in_wires[0]),
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
@ -506,7 +502,6 @@ module fpga_core
.right_width_0_height_0__pin_49_upper(grid_clb_0_right_width_0_height_0__pin_49_upper[0]),
.right_width_0_height_0__pin_49_lower(grid_clb_0_right_width_0_height_0__pin_49_lower[0]),
.bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]),
.bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]),
.ccff_tail(grid_clb_0_ccff_tail[0])
);
@ -516,7 +511,6 @@ module fpga_core
(
.SC_OUT_BOT(scff_Wires[2]),
.SC_IN_TOP(scff_Wires[1]),
.bottom_width_0_height_0__pin_51_(sc_out_wires[0]),
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
@ -537,7 +531,6 @@ module fpga_core
.top_width_0_height_0__pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]),
.top_width_0_height_0__pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]),
.top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]),
.top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]),
.right_width_0_height_0__pin_16_(cby_1__1__1_left_grid_pin_16_[0]),
.right_width_0_height_0__pin_17_(cby_1__1__1_left_grid_pin_17_[0]),
.right_width_0_height_0__pin_18_(cby_1__1__1_left_grid_pin_18_[0]),
@ -598,7 +591,6 @@ module fpga_core
(
.SC_OUT_TOP(scff_Wires[9]),
.SC_IN_BOT(scff_Wires[8]),
.top_width_0_height_0__pin_33_(sc_in_wires[1]),
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
@ -670,7 +662,6 @@ module fpga_core
.right_width_0_height_0__pin_49_upper(grid_clb_2_right_width_0_height_0__pin_49_upper[0]),
.right_width_0_height_0__pin_49_lower(grid_clb_2_right_width_0_height_0__pin_49_lower[0]),
.bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]),
.bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]),
.ccff_tail(grid_clb_2_ccff_tail[0])
);
@ -680,7 +671,6 @@ module fpga_core
(
.SC_OUT_TOP(scff_Wires[11]),
.SC_IN_BOT(scff_Wires[10]),
.bottom_width_0_height_0__pin_51_(sc_out_wires[1]),
.prog_clk(prog_clk[0]),
.Test_en(Test_en[0]),
.clk(clk[0]),
@ -701,7 +691,6 @@ module fpga_core
.top_width_0_height_0__pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]),
.top_width_0_height_0__pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]),
.top_width_0_height_0__pin_32_(direct_interc_2_out[0]),
.top_width_0_height_0__pin_33_(direct_interc_5_out[0]),
.right_width_0_height_0__pin_16_(cby_2__1__1_left_grid_pin_16_[0]),
.right_width_0_height_0__pin_17_(cby_2__1__1_left_grid_pin_17_[0]),
.right_width_0_height_0__pin_18_(cby_2__1__1_left_grid_pin_18_[0]),
@ -1145,8 +1134,6 @@ module fpga_core
(
.SC_OUT_BOT(scff_Wires[3]),
.SC_IN_TOP(scff_Wires[2]),
.CLB_SC_OUT(sc_in_wires[0]),
.CLB_SC_IN(sc_out_wires[0]),
.prog_clk(prog_clk[0]),
.chanx_left_in(sb_0__1__0_chanx_right_out[0:19]),
.chanx_right_in(sb_1__1__0_chanx_left_out[0:19]),
@ -1178,8 +1165,6 @@ module fpga_core
(
.SC_OUT_TOP(scff_Wires[10]),
.SC_IN_BOT(scff_Wires[9]),
.CLB_SC_OUT(sc_in_wires[1]),
.CLB_SC_IN(sc_out_wires[1]),
.prog_clk(prog_clk[0]),
.chanx_left_in(sb_1__1__0_chanx_right_out[0:19]),
.chanx_right_in(sb_2__1__0_chanx_left_out[0:19]),

159
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v
View File

@ -1,86 +1,85 @@
module grid_clb
(
input [0:0] prog_clk,
input [0:0] Test_en,
input [0:0] clk,
input [0:0] top_width_0_height_0__pin_0_,
input [0:0] top_width_0_height_0__pin_1_,
input [0:0] top_width_0_height_0__pin_2_,
input [0:0] top_width_0_height_0__pin_3_,
input [0:0] top_width_0_height_0__pin_4_,
input [0:0] top_width_0_height_0__pin_5_,
input [0:0] top_width_0_height_0__pin_6_,
input [0:0] top_width_0_height_0__pin_7_,
input [0:0] top_width_0_height_0__pin_8_,
input [0:0] top_width_0_height_0__pin_9_,
input [0:0] top_width_0_height_0__pin_10_,
input [0:0] top_width_0_height_0__pin_11_,
input [0:0] top_width_0_height_0__pin_12_,
input [0:0] top_width_0_height_0__pin_13_,
input [0:0] top_width_0_height_0__pin_14_,
input [0:0] top_width_0_height_0__pin_15_,
input [0:0] top_width_0_height_0__pin_32_,
input [0:0] top_width_0_height_0__pin_33_,
input [0:0] right_width_0_height_0__pin_16_,
input [0:0] right_width_0_height_0__pin_17_,
input [0:0] right_width_0_height_0__pin_18_,
input [0:0] right_width_0_height_0__pin_19_,
input [0:0] right_width_0_height_0__pin_20_,
input [0:0] right_width_0_height_0__pin_21_,
input [0:0] right_width_0_height_0__pin_22_,
input [0:0] right_width_0_height_0__pin_23_,
input [0:0] right_width_0_height_0__pin_24_,
input [0:0] right_width_0_height_0__pin_25_,
input [0:0] right_width_0_height_0__pin_26_,
input [0:0] right_width_0_height_0__pin_27_,
input [0:0] right_width_0_height_0__pin_28_,
input [0:0] right_width_0_height_0__pin_29_,
input [0:0] right_width_0_height_0__pin_30_,
input [0:0] right_width_0_height_0__pin_31_,
input [0:0] left_width_0_height_0__pin_52_,
input [0:0] ccff_head,
output [0:0] top_width_0_height_0__pin_34_upper,
output [0:0] top_width_0_height_0__pin_34_lower,
output [0:0] top_width_0_height_0__pin_35_upper,
output [0:0] top_width_0_height_0__pin_35_lower,
output [0:0] top_width_0_height_0__pin_36_upper,
output [0:0] top_width_0_height_0__pin_36_lower,
output [0:0] top_width_0_height_0__pin_37_upper,
output [0:0] top_width_0_height_0__pin_37_lower,
output [0:0] top_width_0_height_0__pin_38_upper,
output [0:0] top_width_0_height_0__pin_38_lower,
output [0:0] top_width_0_height_0__pin_39_upper,
output [0:0] top_width_0_height_0__pin_39_lower,
output [0:0] top_width_0_height_0__pin_40_upper,
output [0:0] top_width_0_height_0__pin_40_lower,
output [0:0] top_width_0_height_0__pin_41_upper,
output [0:0] top_width_0_height_0__pin_41_lower,
output [0:0] right_width_0_height_0__pin_42_upper,
output [0:0] right_width_0_height_0__pin_42_lower,
output [0:0] right_width_0_height_0__pin_43_upper,
output [0:0] right_width_0_height_0__pin_43_lower,
output [0:0] right_width_0_height_0__pin_44_upper,
output [0:0] right_width_0_height_0__pin_44_lower,
output [0:0] right_width_0_height_0__pin_45_upper,
output [0:0] right_width_0_height_0__pin_45_lower,
output [0:0] right_width_0_height_0__pin_46_upper,
output [0:0] right_width_0_height_0__pin_46_lower,
output [0:0] right_width_0_height_0__pin_47_upper,
output [0:0] right_width_0_height_0__pin_47_lower,
output [0:0] right_width_0_height_0__pin_48_upper,
output [0:0] right_width_0_height_0__pin_48_lower,
output [0:0] right_width_0_height_0__pin_49_upper,
output [0:0] right_width_0_height_0__pin_49_lower,
output [0:0] bottom_width_0_height_0__pin_50_,
output [0:0] bottom_width_0_height_0__pin_51_,
output [0:0] ccff_tail,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
( prog_clk, Test_en, clk, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_1_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_3_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_5_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_7_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_9_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_11_, top_width_0_height_0__pin_12_, top_width_0_height_0__pin_13_, top_width_0_height_0__pin_14_, top_width_0_height_0__pin_15_, top_width_0_height_0__pin_32_, top_width_0_height_0__pin_33_, right_width_0_height_0__pin_16_, right_width_0_height_0__pin_17_, right_width_0_height_0__pin_18_, right_width_0_height_0__pin_19_, right_width_0_height_0__pin_20_, right_width_0_height_0__pin_21_, right_width_0_height_0__pin_22_, right_width_0_height_0__pin_23_, right_width_0_height_0__pin_24_, right_width_0_height_0__pin_25_, right_width_0_height_0__pin_26_, right_width_0_height_0__pin_27_, right_width_0_height_0__pin_28_, right_width_0_height_0__pin_29_, right_width_0_height_0__pin_30_, right_width_0_height_0__pin_31_, left_width_0_height_0__pin_52_, ccff_head, top_width_0_height_0__pin_34_upper, top_width_0_height_0__pin_34_lower, top_width_0_height_0__pin_35_upper, top_width_0_height_0__pin_35_lower, top_width_0_height_0__pin_36_upper, top_width_0_height_0__pin_36_lower, top_width_0_height_0__pin_37_upper, top_width_0_height_0__pin_37_lower, top_width_0_height_0__pin_38_upper, top_width_0_height_0__pin_38_lower, top_width_0_height_0__pin_39_upper, top_width_0_height_0__pin_39_lower, top_width_0_height_0__pin_40_upper, top_width_0_height_0__pin_40_lower, top_width_0_height_0__pin_41_upper, top_width_0_height_0__pin_41_lower, right_width_0_height_0__pin_42_upper, right_width_0_height_0__pin_42_lower, right_width_0_height_0__pin_43_upper, right_width_0_height_0__pin_43_lower, right_width_0_height_0__pin_44_upper, right_width_0_height_0__pin_44_lower, right_width_0_height_0__pin_45_upper, right_width_0_height_0__pin_45_lower, right_width_0_height_0__pin_46_upper, right_width_0_height_0__pin_46_lower, right_width_0_height_0__pin_47_upper, right_width_0_height_0__pin_47_lower, right_width_0_height_0__pin_48_upper, right_width_0_height_0__pin_48_lower, right_width_0_height_0__pin_49_upper, right_width_0_height_0__pin_49_lower, bottom_width_0_height_0__pin_50_, bottom_width_0_height_0__pin_51_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:0] Test_en;
input [0:0] clk;
input [0:0] top_width_0_height_0__pin_0_;
input [0:0] top_width_0_height_0__pin_1_;
input [0:0] top_width_0_height_0__pin_2_;
input [0:0] top_width_0_height_0__pin_3_;
input [0:0] top_width_0_height_0__pin_4_;
input [0:0] top_width_0_height_0__pin_5_;
input [0:0] top_width_0_height_0__pin_6_;
input [0:0] top_width_0_height_0__pin_7_;
input [0:0] top_width_0_height_0__pin_8_;
input [0:0] top_width_0_height_0__pin_9_;
input [0:0] top_width_0_height_0__pin_10_;
input [0:0] top_width_0_height_0__pin_11_;
input [0:0] top_width_0_height_0__pin_12_;
input [0:0] top_width_0_height_0__pin_13_;
input [0:0] top_width_0_height_0__pin_14_;
input [0:0] top_width_0_height_0__pin_15_;
input [0:0] top_width_0_height_0__pin_32_;
input [0:0] top_width_0_height_0__pin_33_;
input [0:0] right_width_0_height_0__pin_16_;
input [0:0] right_width_0_height_0__pin_17_;
input [0:0] right_width_0_height_0__pin_18_;
input [0:0] right_width_0_height_0__pin_19_;
input [0:0] right_width_0_height_0__pin_20_;
input [0:0] right_width_0_height_0__pin_21_;
input [0:0] right_width_0_height_0__pin_22_;
input [0:0] right_width_0_height_0__pin_23_;
input [0:0] right_width_0_height_0__pin_24_;
input [0:0] right_width_0_height_0__pin_25_;
input [0:0] right_width_0_height_0__pin_26_;
input [0:0] right_width_0_height_0__pin_27_;
input [0:0] right_width_0_height_0__pin_28_;
input [0:0] right_width_0_height_0__pin_29_;
input [0:0] right_width_0_height_0__pin_30_;
input [0:0] right_width_0_height_0__pin_31_;
input [0:0] left_width_0_height_0__pin_52_;
input [0:0] ccff_head;
output [0:0] top_width_0_height_0__pin_34_upper;
output [0:0] top_width_0_height_0__pin_34_lower;
output [0:0] top_width_0_height_0__pin_35_upper;
output [0:0] top_width_0_height_0__pin_35_lower;
output [0:0] top_width_0_height_0__pin_36_upper;
output [0:0] top_width_0_height_0__pin_36_lower;
output [0:0] top_width_0_height_0__pin_37_upper;
output [0:0] top_width_0_height_0__pin_37_lower;
output [0:0] top_width_0_height_0__pin_38_upper;
output [0:0] top_width_0_height_0__pin_38_lower;
output [0:0] top_width_0_height_0__pin_39_upper;
output [0:0] top_width_0_height_0__pin_39_lower;
output [0:0] top_width_0_height_0__pin_40_upper;
output [0:0] top_width_0_height_0__pin_40_lower;
output [0:0] top_width_0_height_0__pin_41_upper;
output [0:0] top_width_0_height_0__pin_41_lower;
output [0:0] right_width_0_height_0__pin_42_upper;
output [0:0] right_width_0_height_0__pin_42_lower;
output [0:0] right_width_0_height_0__pin_43_upper;
output [0:0] right_width_0_height_0__pin_43_lower;
output [0:0] right_width_0_height_0__pin_44_upper;
output [0:0] right_width_0_height_0__pin_44_lower;
output [0:0] right_width_0_height_0__pin_45_upper;
output [0:0] right_width_0_height_0__pin_45_lower;
output [0:0] right_width_0_height_0__pin_46_upper;
output [0:0] right_width_0_height_0__pin_46_lower;
output [0:0] right_width_0_height_0__pin_47_upper;
output [0:0] right_width_0_height_0__pin_47_lower;
output [0:0] right_width_0_height_0__pin_48_upper;
output [0:0] right_width_0_height_0__pin_48_lower;
output [0:0] right_width_0_height_0__pin_49_upper;
output [0:0] right_width_0_height_0__pin_49_lower;
output [0:0] bottom_width_0_height_0__pin_50_;
output [0:0] bottom_width_0_height_0__pin_51_;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
assign top_width_0_height_0__pin_34_lower[0] = top_width_0_height_0__pin_34_upper[0];
assign top_width_0_height_0__pin_35_lower[0] = top_width_0_height_0__pin_35_upper[0];

176
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v
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@ -1,176 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module grid_io_bottom(prog_clk,
gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_EMBEDDED_IO_SOC_DIR,
top_width_0_height_0__pin_0_,
top_width_0_height_0__pin_2_,
top_width_0_height_0__pin_4_,
top_width_0_height_0__pin_6_,
top_width_0_height_0__pin_8_,
top_width_0_height_0__pin_10_,
ccff_head,
top_width_0_height_0__pin_1_upper,
top_width_0_height_0__pin_1_lower,
top_width_0_height_0__pin_3_upper,
top_width_0_height_0__pin_3_lower,
top_width_0_height_0__pin_5_upper,
top_width_0_height_0__pin_5_lower,
top_width_0_height_0__pin_7_upper,
top_width_0_height_0__pin_7_lower,
top_width_0_height_0__pin_9_upper,
top_width_0_height_0__pin_9_lower,
top_width_0_height_0__pin_11_upper,
top_width_0_height_0__pin_11_lower,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN;
//
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT;
//
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
input [0:0] top_width_0_height_0__pin_0_;
//
input [0:0] top_width_0_height_0__pin_2_;
//
input [0:0] top_width_0_height_0__pin_4_;
//
input [0:0] top_width_0_height_0__pin_6_;
//
input [0:0] top_width_0_height_0__pin_8_;
//
input [0:0] top_width_0_height_0__pin_10_;
//
input [0:0] ccff_head;
//
output [0:0] top_width_0_height_0__pin_1_upper;
//
output [0:0] top_width_0_height_0__pin_1_lower;
//
output [0:0] top_width_0_height_0__pin_3_upper;
//
output [0:0] top_width_0_height_0__pin_3_lower;
//
output [0:0] top_width_0_height_0__pin_5_upper;
//
output [0:0] top_width_0_height_0__pin_5_lower;
//
output [0:0] top_width_0_height_0__pin_7_upper;
//
output [0:0] top_width_0_height_0__pin_7_lower;
//
output [0:0] top_width_0_height_0__pin_9_upper;
//
output [0:0] top_width_0_height_0__pin_9_lower;
//
output [0:0] top_width_0_height_0__pin_11_upper;
//
output [0:0] top_width_0_height_0__pin_11_lower;
//
output [0:0] ccff_tail;
//
//
//
//
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
//
//
//
assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0];
assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0];
assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0];
assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0];
assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0];
assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0];
//
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(top_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_head[0]),
.io_inpad(top_width_0_height_0__pin_1_upper[0]),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0]));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]),
.io_outpad(top_width_0_height_0__pin_2_[0]),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_3_upper[0]),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0]));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]),
.io_outpad(top_width_0_height_0__pin_4_[0]),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_5_upper[0]),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0]));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]),
.io_outpad(top_width_0_height_0__pin_6_[0]),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_7_upper[0]),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0]));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]),
.io_outpad(top_width_0_height_0__pin_8_[0]),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_9_upper[0]),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0]));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[5]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]),
.io_outpad(top_width_0_height_0__pin_10_[0]),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]),
.io_inpad(top_width_0_height_0__pin_11_upper[0]),
.ccff_tail(ccff_tail[0]));
endmodule
//
//

71
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v
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@ -1,71 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module grid_io_left(prog_clk,
gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_EMBEDDED_IO_SOC_DIR,
right_width_0_height_0__pin_0_,
ccff_head,
right_width_0_height_0__pin_1_upper,
right_width_0_height_0__pin_1_lower,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
//
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
//
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
input [0:0] right_width_0_height_0__pin_0_;
//
input [0:0] ccff_head;
//
output [0:0] right_width_0_height_0__pin_1_upper;
//
output [0:0] right_width_0_height_0__pin_1_lower;
//
output [0:0] ccff_tail;
//
//
//
//
//
//
//
assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0];
//
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(right_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_head[0]),
.io_inpad(right_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0]));
endmodule
//
//

71
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v
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@ -1,71 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module grid_io_right(prog_clk,
gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_EMBEDDED_IO_SOC_DIR,
left_width_0_height_0__pin_0_,
ccff_head,
left_width_0_height_0__pin_1_upper,
left_width_0_height_0__pin_1_lower,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
//
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
//
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
input [0:0] left_width_0_height_0__pin_0_;
//
input [0:0] ccff_head;
//
output [0:0] left_width_0_height_0__pin_1_upper;
//
output [0:0] left_width_0_height_0__pin_1_lower;
//
output [0:0] ccff_tail;
//
//
//
//
//
//
//
assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0];
//
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(left_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_head[0]),
.io_inpad(left_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0]));
endmodule
//
//

71
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v
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@ -1,71 +0,0 @@
//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
//
//
module grid_io_top(prog_clk,
gfpga_pad_EMBEDDED_IO_SOC_IN,
gfpga_pad_EMBEDDED_IO_SOC_OUT,
gfpga_pad_EMBEDDED_IO_SOC_DIR,
bottom_width_0_height_0__pin_0_,
ccff_head,
bottom_width_0_height_0__pin_1_upper,
bottom_width_0_height_0__pin_1_lower,
ccff_tail);
//
input [0:0] prog_clk;
//
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
//
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
//
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
//
input [0:0] bottom_width_0_height_0__pin_0_;
//
input [0:0] ccff_head;
//
output [0:0] bottom_width_0_height_0__pin_1_upper;
//
output [0:0] bottom_width_0_height_0__pin_1_lower;
//
output [0:0] ccff_tail;
//
//
//
//
//
//
//
assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0];
//
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk[0]),
.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]),
.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]),
.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]),
.io_outpad(bottom_width_0_height_0__pin_0_[0]),
.ccff_head(ccff_head[0]),
.io_inpad(bottom_width_0_height_0__pin_1_upper[0]),
.ccff_tail(ccff_tail[0]));
endmodule
//
//

89
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v
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@ -1,46 +1,45 @@
module cbx_1__0_
(
input [0:0] prog_clk,
input [0:19] chanx_left_in,
input [0:19] chanx_right_in,
input [0:0] ccff_head,
output [0:19] chanx_left_out,
output [0:19] chanx_right_out,
output [0:0] bottom_grid_pin_0_,
output [0:0] bottom_grid_pin_2_,
output [0:0] bottom_grid_pin_4_,
output [0:0] bottom_grid_pin_6_,
output [0:0] bottom_grid_pin_8_,
output [0:0] bottom_grid_pin_10_,
output [0:0] ccff_tail,
input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN,
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT,
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR,
input [0:0] top_width_0_height_0__pin_0_,
input [0:0] top_width_0_height_0__pin_2_,
input [0:0] top_width_0_height_0__pin_4_,
input [0:0] top_width_0_height_0__pin_6_,
input [0:0] top_width_0_height_0__pin_8_,
input [0:0] top_width_0_height_0__pin_10_,
output [0:0] top_width_0_height_0__pin_1_upper,
output [0:0] top_width_0_height_0__pin_1_lower,
output [0:0] top_width_0_height_0__pin_3_upper,
output [0:0] top_width_0_height_0__pin_3_lower,
output [0:0] top_width_0_height_0__pin_5_upper,
output [0:0] top_width_0_height_0__pin_5_lower,
output [0:0] top_width_0_height_0__pin_7_upper,
output [0:0] top_width_0_height_0__pin_7_lower,
output [0:0] top_width_0_height_0__pin_9_upper,
output [0:0] top_width_0_height_0__pin_9_lower,
output [0:0] top_width_0_height_0__pin_11_upper,
output [0:0] top_width_0_height_0__pin_11_lower,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_2_, bottom_grid_pin_4_, bottom_grid_pin_6_, bottom_grid_pin_8_, bottom_grid_pin_10_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_1_upper, top_width_0_height_0__pin_1_lower, top_width_0_height_0__pin_3_upper, top_width_0_height_0__pin_3_lower, top_width_0_height_0__pin_5_upper, top_width_0_height_0__pin_5_lower, top_width_0_height_0__pin_7_upper, top_width_0_height_0__pin_7_lower, top_width_0_height_0__pin_9_upper, top_width_0_height_0__pin_9_lower, top_width_0_height_0__pin_11_upper, top_width_0_height_0__pin_11_lower, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chanx_left_in;
input [0:19] chanx_right_in;
input [0:0] ccff_head;
output [0:19] chanx_left_out;
output [0:19] chanx_right_out;
output [0:0] bottom_grid_pin_0_;
output [0:0] bottom_grid_pin_2_;
output [0:0] bottom_grid_pin_4_;
output [0:0] bottom_grid_pin_6_;
output [0:0] bottom_grid_pin_8_;
output [0:0] bottom_grid_pin_10_;
output [0:0] ccff_tail;
input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN;
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT;
output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR;
input [0:0] top_width_0_height_0__pin_0_;
input [0:0] top_width_0_height_0__pin_2_;
input [0:0] top_width_0_height_0__pin_4_;
input [0:0] top_width_0_height_0__pin_6_;
input [0:0] top_width_0_height_0__pin_8_;
input [0:0] top_width_0_height_0__pin_10_;
output [0:0] top_width_0_height_0__pin_1_upper;
output [0:0] top_width_0_height_0__pin_1_lower;
output [0:0] top_width_0_height_0__pin_3_upper;
output [0:0] top_width_0_height_0__pin_3_lower;
output [0:0] top_width_0_height_0__pin_5_upper;
output [0:0] top_width_0_height_0__pin_5_lower;
output [0:0] top_width_0_height_0__pin_7_upper;
output [0:0] top_width_0_height_0__pin_7_lower;
output [0:0] top_width_0_height_0__pin_9_upper;
output [0:0] top_width_0_height_0__pin_9_lower;
output [0:0] top_width_0_height_0__pin_11_upper;
output [0:0] top_width_0_height_0__pin_11_lower;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
@ -179,7 +178,7 @@ module cbx_1__0_
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
);
@ -190,7 +189,7 @@ module cbx_1__0_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
);
@ -201,7 +200,7 @@ module cbx_1__0_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
);
@ -212,7 +211,7 @@ module cbx_1__0_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
);
@ -223,7 +222,7 @@ module cbx_1__0_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
);

60
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v
View File

@ -1,37 +1,34 @@
module cbx_1__1_
(
input [0:0] prog_clk,
input [0:19] chanx_left_in,
input [0:19] chanx_right_in,
input [0:0] ccff_head,
output [0:19] chanx_left_out,
output [0:19] chanx_right_out,
output [0:0] bottom_grid_pin_0_,
output [0:0] bottom_grid_pin_1_,
output [0:0] bottom_grid_pin_2_,
output [0:0] bottom_grid_pin_3_,
output [0:0] bottom_grid_pin_4_,
output [0:0] bottom_grid_pin_5_,
output [0:0] bottom_grid_pin_6_,
output [0:0] bottom_grid_pin_7_,
output [0:0] bottom_grid_pin_8_,
output [0:0] bottom_grid_pin_9_,
output [0:0] bottom_grid_pin_10_,
output [0:0] bottom_grid_pin_11_,
output [0:0] bottom_grid_pin_12_,
output [0:0] bottom_grid_pin_13_,
output [0:0] bottom_grid_pin_14_,
output [0:0] bottom_grid_pin_15_,
output [0:0] ccff_tail,
input CLB_SC_IN,
output CLB_SC_OUT,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chanx_left_in;
input [0:19] chanx_right_in;
input [0:0] ccff_head;
output [0:19] chanx_left_out;
output [0:19] chanx_right_out;
output [0:0] bottom_grid_pin_0_;
output [0:0] bottom_grid_pin_1_;
output [0:0] bottom_grid_pin_2_;
output [0:0] bottom_grid_pin_3_;
output [0:0] bottom_grid_pin_4_;
output [0:0] bottom_grid_pin_5_;
output [0:0] bottom_grid_pin_6_;
output [0:0] bottom_grid_pin_7_;
output [0:0] bottom_grid_pin_8_;
output [0:0] bottom_grid_pin_9_;
output [0:0] bottom_grid_pin_10_;
output [0:0] bottom_grid_pin_11_;
output [0:0] bottom_grid_pin_12_;
output [0:0] bottom_grid_pin_13_;
output [0:0] bottom_grid_pin_14_;
output [0:0] bottom_grid_pin_15_;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
@ -120,7 +117,6 @@ module cbx_1__1_
assign chanx_left_out[17] = chanx_right_in[17];
assign chanx_left_out[18] = chanx_right_in[18];
assign chanx_left_out[19] = chanx_right_in[19];
assign CLB_SC_OUT = CLB_SC_IN;
assign SC_IN_TOP = SC_IN_BOT;
assign SC_OUT_TOP = SC_OUT_BOT;

103
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v
View File

@ -1,42 +1,41 @@
module cbx_1__2_
(
input [0:0] prog_clk,
input [0:19] chanx_left_in,
input [0:19] chanx_right_in,
input [0:0] ccff_head,
output [0:19] chanx_left_out,
output [0:19] chanx_right_out,
output [0:0] top_grid_pin_0_,
output [0:0] bottom_grid_pin_0_,
output [0:0] bottom_grid_pin_1_,
output [0:0] bottom_grid_pin_2_,
output [0:0] bottom_grid_pin_3_,
output [0:0] bottom_grid_pin_4_,
output [0:0] bottom_grid_pin_5_,
output [0:0] bottom_grid_pin_6_,
output [0:0] bottom_grid_pin_7_,
output [0:0] bottom_grid_pin_8_,
output [0:0] bottom_grid_pin_9_,
output [0:0] bottom_grid_pin_10_,
output [0:0] bottom_grid_pin_11_,
output [0:0] bottom_grid_pin_12_,
output [0:0] bottom_grid_pin_13_,
output [0:0] bottom_grid_pin_14_,
output [0:0] bottom_grid_pin_15_,
output [0:0] ccff_tail,
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR,
input [0:0] bottom_width_0_height_0__pin_0_,
output [0:0] bottom_width_0_height_0__pin_1_upper,
output [0:0] bottom_width_0_height_0__pin_1_lower,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, top_grid_pin_0_, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, bottom_width_0_height_0__pin_0_, bottom_width_0_height_0__pin_1_upper, bottom_width_0_height_0__pin_1_lower, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chanx_left_in;
input [0:19] chanx_right_in;
input [0:0] ccff_head;
output [0:19] chanx_left_out;
output [0:19] chanx_right_out;
output [0:0] top_grid_pin_0_;
output [0:0] bottom_grid_pin_0_;
output [0:0] bottom_grid_pin_1_;
output [0:0] bottom_grid_pin_2_;
output [0:0] bottom_grid_pin_3_;
output [0:0] bottom_grid_pin_4_;
output [0:0] bottom_grid_pin_5_;
output [0:0] bottom_grid_pin_6_;
output [0:0] bottom_grid_pin_7_;
output [0:0] bottom_grid_pin_8_;
output [0:0] bottom_grid_pin_9_;
output [0:0] bottom_grid_pin_10_;
output [0:0] bottom_grid_pin_11_;
output [0:0] bottom_grid_pin_12_;
output [0:0] bottom_grid_pin_13_;
output [0:0] bottom_grid_pin_14_;
output [0:0] bottom_grid_pin_15_;
output [0:0] ccff_tail;
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
input [0:0] bottom_width_0_height_0__pin_0_;
output [0:0] bottom_width_0_height_0__pin_1_upper;
output [0:0] bottom_width_0_height_0__pin_1_lower;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
@ -228,7 +227,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
);
@ -239,7 +238,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
);
@ -250,7 +249,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
);
@ -261,7 +260,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
);
@ -272,7 +271,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
);
@ -283,7 +282,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
);
@ -294,7 +293,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
);
@ -305,7 +304,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
);
@ -407,7 +406,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
);
@ -418,7 +417,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
);
@ -429,7 +428,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
);
@ -440,7 +439,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
);
@ -451,7 +450,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
);
@ -462,7 +461,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
);
@ -473,7 +472,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
);
@ -484,7 +483,7 @@ module cbx_1__2_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
);

31
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v
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@ -1,22 +1,21 @@
module cby_0__1_
(
input [0:0] prog_clk,
input [0:19] chany_bottom_in,
input [0:19] chany_top_in,
input [0:0] ccff_head,
output [0:19] chany_bottom_out,
output [0:19] chany_top_out,
output [0:0] left_grid_pin_0_,
output [0:0] ccff_tail,
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR,
input [0:0] right_width_0_height_0__pin_0_,
output [0:0] right_width_0_height_0__pin_1_upper,
output [0:0] right_width_0_height_0__pin_1_lower
);
( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_0_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, right_width_0_height_0__pin_0_, right_width_0_height_0__pin_1_upper, right_width_0_height_0__pin_1_lower );
input [0:0] prog_clk;
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] left_grid_pin_0_;
output [0:0] ccff_tail;
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
input [0:0] right_width_0_height_0__pin_0_;
output [0:0] right_width_0_height_0__pin_1_upper;
output [0:0] right_width_0_height_0__pin_1_lower;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;

49
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v
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@ -1,31 +1,30 @@
module cby_1__1_
(
input [0:0] prog_clk,
input [0:19] chany_bottom_in,
input [0:19] chany_top_in,
input [0:0] ccff_head,
output [0:19] chany_bottom_out,
output [0:19] chany_top_out,
output [0:0] left_grid_pin_16_,
output [0:0] left_grid_pin_17_,
output [0:0] left_grid_pin_18_,
output [0:0] left_grid_pin_19_,
output [0:0] left_grid_pin_20_,
output [0:0] left_grid_pin_21_,
output [0:0] left_grid_pin_22_,
output [0:0] left_grid_pin_23_,
output [0:0] left_grid_pin_24_,
output [0:0] left_grid_pin_25_,
output [0:0] left_grid_pin_26_,
output [0:0] left_grid_pin_27_,
output [0:0] left_grid_pin_28_,
output [0:0] left_grid_pin_29_,
output [0:0] left_grid_pin_30_,
output [0:0] left_grid_pin_31_,
output [0:0] ccff_tail
);
( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] left_grid_pin_16_;
output [0:0] left_grid_pin_17_;
output [0:0] left_grid_pin_18_;
output [0:0] left_grid_pin_19_;
output [0:0] left_grid_pin_20_;
output [0:0] left_grid_pin_21_;
output [0:0] left_grid_pin_22_;
output [0:0] left_grid_pin_23_;
output [0:0] left_grid_pin_24_;
output [0:0] left_grid_pin_25_;
output [0:0] left_grid_pin_26_;
output [0:0] left_grid_pin_27_;
output [0:0] left_grid_pin_28_;
output [0:0] left_grid_pin_29_;
output [0:0] left_grid_pin_30_;
output [0:0] left_grid_pin_31_;
output [0:0] ccff_tail;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;

95
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v
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@ -1,38 +1,37 @@
module cby_2__1_
(
input [0:0] prog_clk,
input [0:19] chany_bottom_in,
input [0:19] chany_top_in,
input [0:0] ccff_head,
output [0:19] chany_bottom_out,
output [0:19] chany_top_out,
output [0:0] right_grid_pin_0_,
output [0:0] left_grid_pin_16_,
output [0:0] left_grid_pin_17_,
output [0:0] left_grid_pin_18_,
output [0:0] left_grid_pin_19_,
output [0:0] left_grid_pin_20_,
output [0:0] left_grid_pin_21_,
output [0:0] left_grid_pin_22_,
output [0:0] left_grid_pin_23_,
output [0:0] left_grid_pin_24_,
output [0:0] left_grid_pin_25_,
output [0:0] left_grid_pin_26_,
output [0:0] left_grid_pin_27_,
output [0:0] left_grid_pin_28_,
output [0:0] left_grid_pin_29_,
output [0:0] left_grid_pin_30_,
output [0:0] left_grid_pin_31_,
output [0:0] ccff_tail,
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT,
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR,
input [0:0] left_width_0_height_0__pin_0_,
output [0:0] left_width_0_height_0__pin_1_upper,
output [0:0] left_width_0_height_0__pin_1_lower
);
( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, right_grid_pin_0_, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, left_width_0_height_0__pin_0_, left_width_0_height_0__pin_1_upper, left_width_0_height_0__pin_1_lower );
input [0:0] prog_clk;
input [0:19] chany_bottom_in;
input [0:19] chany_top_in;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chany_top_out;
output [0:0] right_grid_pin_0_;
output [0:0] left_grid_pin_16_;
output [0:0] left_grid_pin_17_;
output [0:0] left_grid_pin_18_;
output [0:0] left_grid_pin_19_;
output [0:0] left_grid_pin_20_;
output [0:0] left_grid_pin_21_;
output [0:0] left_grid_pin_22_;
output [0:0] left_grid_pin_23_;
output [0:0] left_grid_pin_24_;
output [0:0] left_grid_pin_25_;
output [0:0] left_grid_pin_26_;
output [0:0] left_grid_pin_27_;
output [0:0] left_grid_pin_28_;
output [0:0] left_grid_pin_29_;
output [0:0] left_grid_pin_30_;
output [0:0] left_grid_pin_31_;
output [0:0] ccff_tail;
input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT;
output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR;
input [0:0] left_width_0_height_0__pin_0_;
output [0:0] left_width_0_height_0__pin_1_upper;
output [0:0] left_width_0_height_0__pin_1_lower;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
@ -222,7 +221,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3])
);
@ -233,7 +232,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3])
);
@ -244,7 +243,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3])
);
@ -255,7 +254,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3])
);
@ -266,7 +265,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3])
);
@ -277,7 +276,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3])
);
@ -288,7 +287,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3])
);
@ -299,7 +298,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size10_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3])
);
@ -401,7 +400,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3])
);
@ -412,7 +411,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3])
);
@ -423,7 +422,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3])
);
@ -434,7 +433,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3])
);
@ -445,7 +444,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_4_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3])
);
@ -456,7 +455,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_5_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3])
);
@ -467,7 +466,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_6_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3])
);
@ -478,7 +477,7 @@ module cby_2__1_
(
.prog_clk(prog_clk[0]),
.ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]),
.ccff_tail(ccff_tail_mid),
.ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]),
.mem_out(mux_tree_tapbuf_size8_7_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3])
);

31
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v
View File

@ -1,22 +1,21 @@
module sb_0__0_
(
input [0:0] prog_clk,
input [0:19] chany_top_in,
input [0:0] top_left_grid_pin_1_,
input [0:19] chanx_right_in,
input [0:0] right_bottom_grid_pin_1_,
input [0:0] right_bottom_grid_pin_3_,
input [0:0] right_bottom_grid_pin_5_,
input [0:0] right_bottom_grid_pin_7_,
input [0:0] right_bottom_grid_pin_9_,
input [0:0] right_bottom_grid_pin_11_,
input [0:0] ccff_head,
output [0:19] chany_top_out,
output [0:19] chanx_right_out,
output [0:0] ccff_tail
);
( prog_clk, chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_right_out, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_1_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_1_;
input [0:0] right_bottom_grid_pin_3_;
input [0:0] right_bottom_grid_pin_5_;
input [0:0] right_bottom_grid_pin_7_;
input [0:0] right_bottom_grid_pin_9_;
input [0:0] right_bottom_grid_pin_11_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:0] ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;

41
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v
View File

@ -1,27 +1,26 @@
module sb_0__1_
(
input [0:0] prog_clk,
input [0:19] chany_top_in,
input [0:0] top_left_grid_pin_1_,
input [0:19] chanx_right_in,
input [0:0] right_bottom_grid_pin_34_,
input [0:0] right_bottom_grid_pin_35_,
input [0:0] right_bottom_grid_pin_36_,
input [0:0] right_bottom_grid_pin_37_,
input [0:0] right_bottom_grid_pin_38_,
input [0:0] right_bottom_grid_pin_39_,
input [0:0] right_bottom_grid_pin_40_,
input [0:0] right_bottom_grid_pin_41_,
input [0:19] chany_bottom_in,
input [0:0] bottom_left_grid_pin_1_,
input [0:0] ccff_head,
output [0:19] chany_top_out,
output [0:19] chanx_right_out,
output [0:19] chany_bottom_out,
output [0:0] ccff_tail
);
( prog_clk, chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_1_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_1_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:0] ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;

45
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v
View File

@ -1,29 +1,28 @@
module sb_0__2_
(
input [0:0] prog_clk,
input [0:19] chanx_right_in,
input [0:0] right_top_grid_pin_1_,
input [0:0] right_bottom_grid_pin_34_,
input [0:0] right_bottom_grid_pin_35_,
input [0:0] right_bottom_grid_pin_36_,
input [0:0] right_bottom_grid_pin_37_,
input [0:0] right_bottom_grid_pin_38_,
input [0:0] right_bottom_grid_pin_39_,
input [0:0] right_bottom_grid_pin_40_,
input [0:0] right_bottom_grid_pin_41_,
input [0:19] chany_bottom_in,
input [0:0] bottom_left_grid_pin_1_,
input [0:0] ccff_head,
output [0:19] chanx_right_out,
output [0:19] chany_bottom_out,
output [0:0] ccff_tail,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
( prog_clk, chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chanx_right_out, chany_bottom_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chanx_right_in;
input [0:0] right_top_grid_pin_1_;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_1_;
input [0:0] ccff_head;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;

69
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v
View File

@ -1,41 +1,40 @@
module sb_1__0_
(
input [0:0] prog_clk,
input [0:19] chany_top_in,
input [0:0] top_left_grid_pin_42_,
input [0:0] top_left_grid_pin_43_,
input [0:0] top_left_grid_pin_44_,
input [0:0] top_left_grid_pin_45_,
input [0:0] top_left_grid_pin_46_,
input [0:0] top_left_grid_pin_47_,
input [0:0] top_left_grid_pin_48_,
input [0:0] top_left_grid_pin_49_,
input [0:19] chanx_right_in,
input [0:0] right_bottom_grid_pin_1_,
input [0:0] right_bottom_grid_pin_3_,
input [0:0] right_bottom_grid_pin_5_,
input [0:0] right_bottom_grid_pin_7_,
input [0:0] right_bottom_grid_pin_9_,
input [0:0] right_bottom_grid_pin_11_,
input [0:19] chanx_left_in,
input [0:0] left_bottom_grid_pin_1_,
input [0:0] left_bottom_grid_pin_3_,
input [0:0] left_bottom_grid_pin_5_,
input [0:0] left_bottom_grid_pin_7_,
input [0:0] left_bottom_grid_pin_9_,
input [0:0] left_bottom_grid_pin_11_,
input [0:0] ccff_head,
output [0:19] chany_top_out,
output [0:19] chanx_right_out,
output [0:19] chanx_left_out,
output [0:0] ccff_tail,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_right_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_1_;
input [0:0] right_bottom_grid_pin_3_;
input [0:0] right_bottom_grid_pin_5_;
input [0:0] right_bottom_grid_pin_7_;
input [0:0] right_bottom_grid_pin_9_;
input [0:0] right_bottom_grid_pin_11_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_1_;
input [0:0] left_bottom_grid_pin_3_;
input [0:0] left_bottom_grid_pin_5_;
input [0:0] left_bottom_grid_pin_7_;
input [0:0] left_bottom_grid_pin_9_;
input [0:0] left_bottom_grid_pin_11_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:3] mux_tree_tapbuf_size11_0_sram;
wire [0:3] mux_tree_tapbuf_size11_0_sram_inv;

89
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v
View File

@ -1,51 +1,50 @@
module sb_1__1_
(
input [0:0] prog_clk,
input [0:19] chany_top_in,
input [0:0] top_left_grid_pin_42_,
input [0:0] top_left_grid_pin_43_,
input [0:0] top_left_grid_pin_44_,
input [0:0] top_left_grid_pin_45_,
input [0:0] top_left_grid_pin_46_,
input [0:0] top_left_grid_pin_47_,
input [0:0] top_left_grid_pin_48_,
input [0:0] top_left_grid_pin_49_,
input [0:19] chanx_right_in,
input [0:0] right_bottom_grid_pin_34_,
input [0:0] right_bottom_grid_pin_35_,
input [0:0] right_bottom_grid_pin_36_,
input [0:0] right_bottom_grid_pin_37_,
input [0:0] right_bottom_grid_pin_38_,
input [0:0] right_bottom_grid_pin_39_,
input [0:0] right_bottom_grid_pin_40_,
input [0:0] right_bottom_grid_pin_41_,
input [0:19] chany_bottom_in,
input [0:0] bottom_left_grid_pin_42_,
input [0:0] bottom_left_grid_pin_43_,
input [0:0] bottom_left_grid_pin_44_,
input [0:0] bottom_left_grid_pin_45_,
input [0:0] bottom_left_grid_pin_46_,
input [0:0] bottom_left_grid_pin_47_,
input [0:0] bottom_left_grid_pin_48_,
input [0:0] bottom_left_grid_pin_49_,
input [0:19] chanx_left_in,
input [0:0] left_bottom_grid_pin_34_,
input [0:0] left_bottom_grid_pin_35_,
input [0:0] left_bottom_grid_pin_36_,
input [0:0] left_bottom_grid_pin_37_,
input [0:0] left_bottom_grid_pin_38_,
input [0:0] left_bottom_grid_pin_39_,
input [0:0] left_bottom_grid_pin_40_,
input [0:0] left_bottom_grid_pin_41_,
input [0:0] ccff_head,
output [0:19] chany_top_out,
output [0:19] chanx_right_out,
output [0:19] chany_bottom_out,
output [0:19] chanx_left_out,
output [0:0] ccff_tail
);
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:19] chanx_right_in;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;

81
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v
View File

@ -1,47 +1,46 @@
module sb_1__2_
(
input [0:0] prog_clk,
input [0:19] chanx_right_in,
input [0:0] right_top_grid_pin_1_,
input [0:0] right_bottom_grid_pin_34_,
input [0:0] right_bottom_grid_pin_35_,
input [0:0] right_bottom_grid_pin_36_,
input [0:0] right_bottom_grid_pin_37_,
input [0:0] right_bottom_grid_pin_38_,
input [0:0] right_bottom_grid_pin_39_,
input [0:0] right_bottom_grid_pin_40_,
input [0:0] right_bottom_grid_pin_41_,
input [0:19] chany_bottom_in,
input [0:0] bottom_left_grid_pin_42_,
input [0:0] bottom_left_grid_pin_43_,
input [0:0] bottom_left_grid_pin_44_,
input [0:0] bottom_left_grid_pin_45_,
input [0:0] bottom_left_grid_pin_46_,
input [0:0] bottom_left_grid_pin_47_,
input [0:0] bottom_left_grid_pin_48_,
input [0:0] bottom_left_grid_pin_49_,
input [0:19] chanx_left_in,
input [0:0] left_top_grid_pin_1_,
input [0:0] left_bottom_grid_pin_34_,
input [0:0] left_bottom_grid_pin_35_,
input [0:0] left_bottom_grid_pin_36_,
input [0:0] left_bottom_grid_pin_37_,
input [0:0] left_bottom_grid_pin_38_,
input [0:0] left_bottom_grid_pin_39_,
input [0:0] left_bottom_grid_pin_40_,
input [0:0] left_bottom_grid_pin_41_,
input [0:0] ccff_head,
output [0:19] chanx_right_out,
output [0:19] chany_bottom_out,
output [0:19] chanx_left_out,
output [0:0] ccff_tail,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
( prog_clk, chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chanx_right_in;
input [0:0] right_top_grid_pin_1_;
input [0:0] right_bottom_grid_pin_34_;
input [0:0] right_bottom_grid_pin_35_;
input [0:0] right_bottom_grid_pin_36_;
input [0:0] right_bottom_grid_pin_37_;
input [0:0] right_bottom_grid_pin_38_;
input [0:0] right_bottom_grid_pin_39_;
input [0:0] right_bottom_grid_pin_40_;
input [0:0] right_bottom_grid_pin_41_;
input [0:19] chany_bottom_in;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_top_grid_pin_1_;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chanx_right_out;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;

47
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v
View File

@ -1,30 +1,29 @@
module sb_2__0_
(
input [0:0] prog_clk,
input [0:19] chany_top_in,
input [0:0] top_left_grid_pin_42_,
input [0:0] top_left_grid_pin_43_,
input [0:0] top_left_grid_pin_44_,
input [0:0] top_left_grid_pin_45_,
input [0:0] top_left_grid_pin_46_,
input [0:0] top_left_grid_pin_47_,
input [0:0] top_left_grid_pin_48_,
input [0:0] top_left_grid_pin_49_,
input [0:0] top_right_grid_pin_1_,
input [0:19] chanx_left_in,
input [0:0] left_bottom_grid_pin_1_,
input [0:0] left_bottom_grid_pin_3_,
input [0:0] left_bottom_grid_pin_5_,
input [0:0] left_bottom_grid_pin_7_,
input [0:0] left_bottom_grid_pin_9_,
input [0:0] left_bottom_grid_pin_11_,
input [0:0] ccff_head,
output [0:19] chany_top_out,
output [0:19] chanx_left_out,
output [0:0] ccff_tail
);
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_left_out, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:0] top_right_grid_pin_1_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_1_;
input [0:0] left_bottom_grid_pin_3_;
input [0:0] left_bottom_grid_pin_5_;
input [0:0] left_bottom_grid_pin_7_;
input [0:0] left_bottom_grid_pin_9_;
input [0:0] left_bottom_grid_pin_11_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;

73
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v
View File

@ -1,43 +1,42 @@
module sb_2__1_
(
input [0:0] prog_clk,
input [0:19] chany_top_in,
input [0:0] top_left_grid_pin_42_,
input [0:0] top_left_grid_pin_43_,
input [0:0] top_left_grid_pin_44_,
input [0:0] top_left_grid_pin_45_,
input [0:0] top_left_grid_pin_46_,
input [0:0] top_left_grid_pin_47_,
input [0:0] top_left_grid_pin_48_,
input [0:0] top_left_grid_pin_49_,
input [0:0] top_right_grid_pin_1_,
input [0:19] chany_bottom_in,
input [0:0] bottom_right_grid_pin_1_,
input [0:0] bottom_left_grid_pin_42_,
input [0:0] bottom_left_grid_pin_43_,
input [0:0] bottom_left_grid_pin_44_,
input [0:0] bottom_left_grid_pin_45_,
input [0:0] bottom_left_grid_pin_46_,
input [0:0] bottom_left_grid_pin_47_,
input [0:0] bottom_left_grid_pin_48_,
input [0:0] bottom_left_grid_pin_49_,
input [0:19] chanx_left_in,
input [0:0] left_bottom_grid_pin_34_,
input [0:0] left_bottom_grid_pin_35_,
input [0:0] left_bottom_grid_pin_36_,
input [0:0] left_bottom_grid_pin_37_,
input [0:0] left_bottom_grid_pin_38_,
input [0:0] left_bottom_grid_pin_39_,
input [0:0] left_bottom_grid_pin_40_,
input [0:0] left_bottom_grid_pin_41_,
input [0:0] ccff_head,
output [0:19] chany_top_out,
output [0:19] chany_bottom_out,
output [0:19] chanx_left_out,
output [0:0] ccff_tail
);
( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chany_bottom_out, chanx_left_out, ccff_tail );
input [0:0] prog_clk;
input [0:19] chany_top_in;
input [0:0] top_left_grid_pin_42_;
input [0:0] top_left_grid_pin_43_;
input [0:0] top_left_grid_pin_44_;
input [0:0] top_left_grid_pin_45_;
input [0:0] top_left_grid_pin_46_;
input [0:0] top_left_grid_pin_47_;
input [0:0] top_left_grid_pin_48_;
input [0:0] top_left_grid_pin_49_;
input [0:0] top_right_grid_pin_1_;
input [0:19] chany_bottom_in;
input [0:0] bottom_right_grid_pin_1_;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chany_top_out;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;

61
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v
View File

@ -1,37 +1,36 @@
module sb_2__2_
(
input [0:0] prog_clk,
input [0:19] chany_bottom_in,
input [0:0] bottom_right_grid_pin_1_,
input [0:0] bottom_left_grid_pin_42_,
input [0:0] bottom_left_grid_pin_43_,
input [0:0] bottom_left_grid_pin_44_,
input [0:0] bottom_left_grid_pin_45_,
input [0:0] bottom_left_grid_pin_46_,
input [0:0] bottom_left_grid_pin_47_,
input [0:0] bottom_left_grid_pin_48_,
input [0:0] bottom_left_grid_pin_49_,
input [0:19] chanx_left_in,
input [0:0] left_top_grid_pin_1_,
input [0:0] left_bottom_grid_pin_34_,
input [0:0] left_bottom_grid_pin_35_,
input [0:0] left_bottom_grid_pin_36_,
input [0:0] left_bottom_grid_pin_37_,
input [0:0] left_bottom_grid_pin_38_,
input [0:0] left_bottom_grid_pin_39_,
input [0:0] left_bottom_grid_pin_40_,
input [0:0] left_bottom_grid_pin_41_,
input [0:0] ccff_head,
output [0:19] chany_bottom_out,
output [0:19] chanx_left_out,
output [0:0] ccff_tail,
input SC_IN_TOP,
input SC_IN_BOT,
output SC_OUT_TOP,
output SC_OUT_BOT
);
( prog_clk, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT );
input [0:0] prog_clk;
input [0:19] chany_bottom_in;
input [0:0] bottom_right_grid_pin_1_;
input [0:0] bottom_left_grid_pin_42_;
input [0:0] bottom_left_grid_pin_43_;
input [0:0] bottom_left_grid_pin_44_;
input [0:0] bottom_left_grid_pin_45_;
input [0:0] bottom_left_grid_pin_46_;
input [0:0] bottom_left_grid_pin_47_;
input [0:0] bottom_left_grid_pin_48_;
input [0:0] bottom_left_grid_pin_49_;
input [0:19] chanx_left_in;
input [0:0] left_top_grid_pin_1_;
input [0:0] left_bottom_grid_pin_34_;
input [0:0] left_bottom_grid_pin_35_;
input [0:0] left_bottom_grid_pin_36_;
input [0:0] left_bottom_grid_pin_37_;
input [0:0] left_bottom_grid_pin_38_;
input [0:0] left_bottom_grid_pin_39_;
input [0:0] left_bottom_grid_pin_40_;
input [0:0] left_bottom_grid_pin_41_;
input [0:0] ccff_head;
output [0:19] chany_bottom_out;
output [0:19] chanx_left_out;
output [0:0] ccff_tail;
input SC_IN_TOP;
input SC_IN_BOT;
output SC_OUT_TOP;
output SC_OUT_BOT;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;

29
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/std_cell_extract.v
View File

@ -1,29 +0,0 @@
`timescale 1ns/1ps
//
//
//
//
//
//
//
//
//
module GPIO (A, IE, OE, Y, in, out, mem_out);
output A;
output IE;
output OE;
output Y;
input in;
output out;
input mem_out;
assign A = in;
assign out = Y;
assign IE = mem_out;
sky130_fd_sc_hd__inv_1 ie_oe_inv (
.A (mem_out),
.Y (OE) );
endmodule

2
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml
View File

@ -2,7 +2,7 @@
- Fabric bitstream
- Author: Xifan TANG
- Organization: University of Utah
- Date: Fri Nov 6 14:45:09 2020
- Date: Sun Nov 8 17:53:57 2020
-->
<fabric_bitstream>

2
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml
View File

@ -2,7 +2,7 @@
- Architecture independent bitstream
- Author: Xifan TANG
- Organization: University of Utah
- Date: Fri Nov 6 14:45:09 2020
- Date: Sun Nov 8 17:53:56 2020
-->
<bitstream_block name="fpga_top" hierarchy_level="0">

62
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log
View File

@ -83,7 +83,7 @@ Warning 18: [LINE 618] false logically-equivalent pin clb[0].I6[1].
Warning 19: [LINE 618] false logically-equivalent pin clb[0].I6[2].
Warning 20: [LINE 624] false logically-equivalent pin clb[0].I7[1].
Warning 21: [LINE 624] false logically-equivalent pin clb[0].I7[2].
# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB)
# Building complex block graph took 0.00 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB)
# Load circuit
# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB)
# Clean circuit
@ -250,12 +250,12 @@ Device Utilization: 0.25 (target 1.00)
Netlist conversion complete.
# Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB)
# Packing took 0.00 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB)
# Load Packing
Begin loading packed FPGA netlist file.
Netlist generated from file 'top.net'.
Detected 0 constant generators (to see names run with higher pack verbosity)
Finished loading packed FPGA netlist file (took 0.01 seconds).
Finished loading packed FPGA netlist file (took 0 seconds).
Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
# Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB)
Warning 35: Netlist contains 0 global net to non-global architecture pin connections
@ -301,7 +301,7 @@ Device Utilization: 0.25 (target 1.00)
Physical Tile clb:
Block Utilization: 0.25 Logical Block: clb
## Build Device Grid took 0.00 seconds (max_rss 10.7 MiB, delta_rss +0.0 MiB)
## Build Device Grid took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph
X-direction routing channel width is 40
Y-direction routing channel width is 40
@ -309,10 +309,10 @@ Warning 40: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pi
Warning 41: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 42: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 43: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
## Build tileable routing resource graph took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB)
## Build tileable routing resource graph took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
RR Graph Nodes: 756
RR Graph Edges: 2930
# Create Device took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB)
# Create Device took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Placement
## Computing placement delta delay look-up
@ -321,12 +321,12 @@ Warning 44: in check_rr_node: RR node: 119 type: OPIN location: (1,1) pin: 50 pi
Warning 45: in check_rr_node: RR node: 120 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 46: in check_rr_node: RR node: 327 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 47: in check_rr_node: RR node: 328 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
### Build routing resource graph took 0.00 seconds (max_rss 11.2 MiB, delta_rss +0.0 MiB)
### Build routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
RR Graph Nodes: 756
RR Graph Edges: 2428
### Computing delta delays
### Computing delta delays took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.0 MiB)
## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB)
### Computing delta delays took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
## Computing placement delta delay look-up took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
There are 3 point to point connections in this circuit.
@ -440,7 +440,7 @@ Placement total # of swap attempts: 292
Swaps aborted : 0 ( 0.0 %)
Aborted Move Reasons:
# Placement took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.5 MiB)
# Placement took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Routing
## Build tileable routing resource graph
@ -450,7 +450,7 @@ Warning 48: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pi
Warning 49: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 50: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
Warning 51: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
## Build tileable routing resource graph took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
RR Graph Nodes: 756
RR Graph Edges: 2930
Confirming router algorithm: TIMING_DRIVEN.
@ -464,7 +464,7 @@ Restoring best routing
Critical path: 0.86731 ns
Successfully routed after 2 routing iterations.
Router Stats: total_nets_routed: 4 total_connections_routed: 4 total_heap_pushes: 289 total_heap_pops: 187
# Routing took 0.01 seconds (max_rss 11.9 MiB, delta_rss +0.2 MiB)
# Routing took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Checking to ensure routing is legal...
Completed routing consistency check successfully.
@ -562,9 +562,9 @@ Setup slack histogram:
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
[ -8.7e-10: -8.7e-10) 0 ( 0.0%) |
Timing analysis took 0.000428495 seconds (0.000379131 STA, 4.9364e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined).
Timing analysis took 0.000351611 seconds (0.000312774 STA, 3.8837e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined).
VPR suceeded
The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB)
The entire flow of VPR took 0.07 seconds (max_rss 12.7 MiB)
Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
@ -578,10 +578,10 @@ Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be def
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree_tapbuf' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'frac_lut4' port 'sram')
Read OpenFPGA architecture took 0.00 seconds (max_rss 12.0 MiB, delta_rss +0.1 MiB)
Read OpenFPGA architecture took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Check circuit library
Checking circuit library passed.
Check circuit library took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
Check circuit library took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Found 0 errors when checking configurable memory circuit models!
Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
@ -590,7 +590,7 @@ Confirm selected options when call command 'read_openfpga_simulation_setting':
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
Read OpenFPGA simulation settings
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges
@ -633,7 +633,7 @@ Done with 18 nodes mapping
[88%] Backannotated GSB[2][1]
[100%] Backannotated GSB[2][2]
Backannotated 9 General Switch Blocks (GSBs).
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
[11%] Sorted edges for GSB[0][0]
[22%] Sorted edges for GSB[0][1]
@ -645,14 +645,14 @@ Backannotated 9 General Switch Blocks (GSBs).
[88%] Sorted edges for GSB[2][1]
[100%] Sorted edges for GSB[2][2]
Sorted edges for 9 General Switch Blocks (GSBs).
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB)
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Build a library of physical multiplexers
Built a multiplexer library of 15 physical multiplexers.
Maximum multiplexer size is 17.
# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB)
# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Build the annotation about direct connection between tiles
Built 6 tile-to-tile direct connections
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB)
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Building annotation for mapped blocks on grid locations...Done
User specified the operating clock frequency to use VPR results
Use VPR critical path delay 1.04077e-18 [ns] with a 20 [%] slack in OpenFPGA.
@ -662,7 +662,7 @@ Average net density: 0.42
Median net density: 0.00
Average net density after weighting: 0.42
Will apply 2 operating clock cycles to simulations
Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.3 MiB)
Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml
@ -676,7 +676,7 @@ Confirm selected options when call command 'build_fabric':
--verbose: off
Identify unique General Switch Blocks (GSBs)
Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%)
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB)
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
Read Fabric Key
Read Fabric Key took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
@ -691,7 +691,7 @@ Build fabric module graph
# Build local encoder (for multiplexers) modules
# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB)
# Building multiplexer modules
# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB)
# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.2 MiB)
# Build Look-Up Table (LUT) modules
# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.3 MiB)
# Build wire modules
@ -703,7 +703,7 @@ Building logical tiles...Done
Building physical tiles...Done
# Build grid modules took 0.00 seconds (max_rss 13.7 MiB, delta_rss +0.5 MiB)
# Build unique routing modules...
# Build unique routing modules... took 0.02 seconds (max_rss 16.5 MiB, delta_rss +2.8 MiB)
# Build unique routing modules... took 0.01 seconds (max_rss 16.5 MiB, delta_rss +2.8 MiB)
# Build FPGA fabric module
## Add grid instances to top module
## Add grid instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB)
@ -720,7 +720,7 @@ Building physical tiles...Done
## Add module nets for configuration buses
## Add module nets for configuration buses took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
# Build FPGA fabric module took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.8 MiB)
Build fabric module graph took 0.03 seconds (max_rss 17.3 MiB, delta_rss +4.6 MiB)
Build fabric module graph took 0.02 seconds (max_rss 17.3 MiB, delta_rss +4.6 MiB)
Create I/O location mapping for top module
Create I/O location mapping for top module took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
@ -756,7 +756,7 @@ Build fabric-independent bitstream for implementation 'top'
took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
Warning 56: Directory path is empty and nothing will be created.
Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.03 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.02 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB)
Command line to execute: build_fabric_bitstream
@ -777,7 +777,7 @@ Confirm selected options when call command 'write_fabric_bitstream':
--verbose: off
Warning 57: Directory path is empty and nothing will be created.
Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit'
Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB)
Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.01 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml
@ -849,7 +849,7 @@ Building physical tiles...Done
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
Written 73 Verilog modules in total
Write Verilog netlists for FPGA fabric
took 0.16 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB)
took 0.17 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB)
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
@ -879,7 +879,7 @@ Succeed to create directory './SimulationDeck'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
Write Verilog testbenches for FPGA fabric
took 0.04 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
took 0.03 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB)
Command line to execute: exit
@ -887,6 +887,6 @@ Confirm selected options when call command 'exit':
Finish execution with 0 errors
The entire OpenFPGA flow took 0.25 seconds
The entire OpenFPGA flow took 0.19 seconds
Thank you for using OpenFPGA!

7
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl
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@ -1,5 +1,5 @@
set DIE_HEIGHT 1000
set DIE_WIDTH 1000
set DIE_HEIGHT 700
set DIE_WIDTH 700
set DESIGN_NAME fpga_core
set TASK_NAME FPGA22_HIER_SKY_task
set VERILOG_PROJ_DIR FPGA22_HIER_SKY_Verilog
@ -7,6 +7,7 @@ set FPGA_ROW 2
set FPGA_COL 2
set INIT_DESIGN_INPUT DP_RM_NDM
set TECHNOLOGY skywater
set DP_BLOCK_REFS [list sb_0__0_ sb_0__1_ sb_0__2_ sb_1__0_ sb_1__1_ sb_1__2_ sb_2__0_ sb_2__1_ sb_2__2_ cbx_1__0_ cbx_1__1_ cbx_1__2_ cby_0__1_ cby_1__1_ grid_clb grid_io_bottom grid_io_left grid_io_right grid_io_top];
set DP_BLOCK_REFS [list sb_0__0_ sb_0__1_ sb_0__2_ sb_1__0_ sb_1__1_ sb_1__2_ sb_2__0_ sb_2__1_ sb_2__2_ cbx_1__0_ cbx_1__1_ cbx_1__2_ cby_0__1_ cby_1__1_ cby_2__1_ grid_clb];
set DP_FLOW "hier";
set DESIGN_STYLE "hier";
set STANDARD_CELLS sc_hd;

29
FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/std_cell_extract.v
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@ -1,29 +0,0 @@
`timescale 1ns/1ps
//
//
//
//
//
//
//
//
//
module GPIO (A, IE, OE, Y, in, out, mem_out);
output A;
output IE;
output OE;
output Y;
input in;
output out;
input mem_out;
assign A = in;
assign out = Y;
assign IE = mem_out;
sky130_fd_sc_hd__inv_1 ie_oe_inv (
.A (mem_out),
.Y (OE) );
endmodule

11
FPGA22_HIER_SKY_PNR/README.md
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@ -5,11 +5,12 @@ FPGA22_HIER_SKY_PNR
Updates
-------------------
- **Merged `grid_io` modules with connection blocks**
- **Pre-routed scan chain signals**
- **Created `carry_chain` feedthrough between `grid_clb` modules**
- Prerouting global signals (`Test_en`)
- Prerouting clock signals
- Merged `grid_io` modules with connection blocks
- Pre-routed scan chain signals
- Created `carry_chain` feedthrough between `grid_clb` modules
- **Prerouting global signals (`Test_en`)**
- **Prerouting clock signals**
- **Enabled Feed through generation for clock**
Directory Structure
-------------------

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FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv
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@ -1,18 +1,18 @@
| Module | Util| Area| Sites| Insts| Std_Cells
|--------------------|----------|-----------------|-------|-------|-------
| sb_0__0_ | 37.06 | 6606.336000 | 5280 | 1 | 85
| sb_0__1_ | 61.64 | 7687.372800 | 6144 | 1 | 116
| sb_0__2_ | 42.08 | 6606.336000 | 5280 | 1 | 85
| sb_1__0_ | 64.92 | 7807.488000 | 6240 | 1 | 125
| sb_1__1_ | 81.63 | 8888.524800 | 7104 | 1 | 117
| sb_1__2_ | 69.36 | 7807.488000 | 6240 | 1 | 136
| sb_2__0_ | 50.93 | 6606.336000 | 5280 | 1 | 94
| sb_2__1_ | 73.86 | 7687.372800 | 6144 | 1 | 123
| sb_2__2_ | 58.11 | 6606.336000 | 5280 | 1 | 95
| cbx_1__0_ | 60.07 | 5044.838400 | 4032 | 2 | 130
| cbx_1__1_ | 79.61 | 5044.838400 | 4032 | 2 | 86
| cbx_1__2_ | 81.82 | 5044.838400 | 4032 | 2 | 82
| cby_0__1_ | 30.11 | 5044.838400 | 4032 | 2 | 109
| cby_1__1_ | 80.46 | 5044.838400 | 4032 | 2 | 88
| cby_2__1_ | 67.51 | 5044.838400 | 4032 | 2 | 38
| grid_clb_1__1_ | 75.03 | 12411.904000 | 9920 | 4 | 56
| sb_0__0_ | 27.75 | 9068.697600 | 7248 | 1 | 95
| sb_0__1_ | 51.68 | 9809.408000 | 7840 | 1 | 138
| sb_0__2_ | 31.95 | 9068.697600 | 7248 | 1 | 96
| sb_1__0_ | 46.31 | 11471.001600 | 9168 | 1 | 150
| sb_1__1_ | 66.68 | 12211.712000 | 9760 | 1 | 185
| sb_1__2_ | 48.12 | 11471.001600 | 9168 | 1 | 140
| sb_2__0_ | 40.31 | 9068.697600 | 7248 | 1 | 107
| sb_2__1_ | 60.96 | 9809.408000 | 7840 | 1 | 151
| sb_2__2_ | 41.16 | 9068.697600 | 7248 | 1 | 89
| cbx_1__0_ | 54.01 | 5925.683200 | 4736 | 2 | 140
| cbx_1__1_ | 74.16 | 5925.683200 | 4736 | 2 | 112
| cbx_1__2_ | 76.12 | 5925.683200 | 4736 | 2 | 104
| cby_0__1_ | 29.85 | 5184.972800 | 4144 | 2 | 106
| cby_1__1_ | 79.92 | 5184.972800 | 4144 | 2 | 95
| cby_2__1_ | 80.91 | 5184.972800 | 4144 | 2 | 87
| grid_clb_1__1_ | 76.73 | 12071.577600 | 9648 | 4 | 52

1 | Module | Util| Area| Sites| Insts| Std_Cells
2 |--------------------|----------|-----------------|-------|-------|-------
3 | sb_0__0_ | 37.06 | 6606.336000 | 5280 | 1 | 85 | sb_0__0_ | 27.75 | 9068.697600 | 7248 | 1 | 95
4 | sb_0__1_ | 61.64 | 7687.372800 | 6144 | 1 | 116 | sb_0__1_ | 51.68 | 9809.408000 | 7840 | 1 | 138
5 | sb_0__2_ | 42.08 | 6606.336000 | 5280 | 1 | 85 | sb_0__2_ | 31.95 | 9068.697600 | 7248 | 1 | 96
6 | sb_1__0_ | 64.92 | 7807.488000 | 6240 | 1 | 125 | sb_1__0_ | 46.31 | 11471.001600 | 9168 | 1 | 150
7 | sb_1__1_ | 81.63 | 8888.524800 | 7104 | 1 | 117 | sb_1__1_ | 66.68 | 12211.712000 | 9760 | 1 | 185
8 | sb_1__2_ | 69.36 | 7807.488000 | 6240 | 1 | 136 | sb_1__2_ | 48.12 | 11471.001600 | 9168 | 1 | 140
9 | sb_2__0_ | 50.93 | 6606.336000 | 5280 | 1 | 94 | sb_2__0_ | 40.31 | 9068.697600 | 7248 | 1 | 107
10 | sb_2__1_ | 73.86 | 7687.372800 | 6144 | 1 | 123 | sb_2__1_ | 60.96 | 9809.408000 | 7840 | 1 | 151
11 | sb_2__2_ | 58.11 | 6606.336000 | 5280 | 1 | 95 | sb_2__2_ | 41.16 | 9068.697600 | 7248 | 1 | 89
12 | cbx_1__0_ | 60.07 | 5044.838400 | 4032 | 2 | 130 | cbx_1__0_ | 54.01 | 5925.683200 | 4736 | 2 | 140
13 | cbx_1__1_ | 79.61 | 5044.838400 | 4032 | 2 | 86 | cbx_1__1_ | 74.16 | 5925.683200 | 4736 | 2 | 112
14 | cbx_1__2_ | 81.82 | 5044.838400 | 4032 | 2 | 82 | cbx_1__2_ | 76.12 | 5925.683200 | 4736 | 2 | 104
15 | cby_0__1_ | 30.11 | 5044.838400 | 4032 | 2 | 109 | cby_0__1_ | 29.85 | 5184.972800 | 4144 | 2 | 106
16 | cby_1__1_ | 80.46 | 5044.838400 | 4032 | 2 | 88 | cby_1__1_ | 79.92 | 5184.972800 | 4144 | 2 | 95
17 | cby_2__1_ | 67.51 | 5044.838400 | 4032 | 2 | 38 | cby_2__1_ | 80.91 | 5184.972800 | 4144 | 2 | 87
18 | grid_clb_1__1_ | 75.03 | 12411.904000 | 9920 | 4 | 56 | grid_clb_1__1_ | 76.73 | 12071.577600 | 9648 | 4 | 52

31
FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv Normal file
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@ -0,0 +1,31 @@
Ref Name Total Area Utilization_% Instance Count
----------------------------------------------------------------------------------------------------
sky130_fd_sc_hd__mux2_1 33410.793600 6.86 2967
sky130_fd_sc_hd__dfxbp_1 31285.004800 6.43 1316
sky130_fd_sc_hd__dlymetal6s2s_1 9258.880000 1.90 740
sky130_fd_sc_hd__dlymetal6s6s_1 9071.200000 1.86 725
sky130_fd_sc_hd__dlygate4sd3_1 5695.462400 1.17 569
sky130_fd_sc_hd__buf_4 2552.448000 0.52 340
sky130_fd_sc_hd__dlygate4sd2_1 1769.196800 0.36 202
sky130_fd_sc_hd__sdfxtp_1 1681.612800 0.35 64
sky130_fd_sc_hd__mux2_8 1208.659200 0.25 46
sky130_fd_sc_hd__dlygate4sd1_1 613.088000 0.13 70
sky130_fd_sc_hd__buf_2 375.360000 0.08 75
sky130_fd_sc_hd__inv_1 375.360000 0.08 100
sky130_fd_sc_hd__conb_1 326.563200 0.07 87
sky130_fd_sc_hd__or2_0 200.192000 0.04 32
sky130_fd_sc_hd__buf_6 135.129600 0.03 12
sky130_fd_sc_hd__buf_12 80.076800 0.02 4
sky130_fd_sc_hd__buf_8 75.072000 0.02 5
sky130_fd_sc_hd__clkbuf_1 60.057600 0.01 16
sky130_fd_sc_hd__clkinv_16 30.028800 0.01 1
sky130_fd_sc_hd__clkdlybuf4s50_2 22.521600 0.00 2
sky130_fd_sc_hd__clkinvlp_4 22.521600 0.00 3
sky130_fd_sc_hd__clkinvlp_2 20.019200 0.00 4
sky130_fd_sc_hd__clkinv_4 8.758400 0.00 1
sky130_fd_sc_hd__inv_4 6.256000 0.00 1
sky130_fd_sc_hd__clkinv_2 5.004800 0.00 1
sky130_fd_sc_hd__inv_2 3.753600 0.00 1
FPGA_BBOX_AREA 229900.4928
CORE_BBOX_AREA 486866.944
FPGA_BBOX_UTIL 47.2203947368
Can't render this file because it has a wrong number of fields in line 2.

22
FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt
View File

@ -6,7 +6,7 @@ Report : clock timing
-setup
Design : fpga_core
Version: P-2019.03-SP4
Date : Fri Nov 6 22:19:36 2020
Date : Sun Nov 8 18:28:15 2020
****************************************
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
@ -16,7 +16,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
--- Latency ---
Clock Pin Trans Source Offset Network Total Corner
---------------------------------------------------------------------------------------------------
grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.061 0.000 -- 0.039 0.039 rp-+ nominal
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.162 0.000 -- 0.429 0.429 rp-+ nominal
---------------------------------------------------------------------------------------------------
Mode: full_chip
@ -25,7 +25,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
--- Latency ---
Clock Pin Trans Source Offset Network Total Corner
---------------------------------------------------------------------------------------------------
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.187 0.000 -- 5.545 5.545 rp-+ nominal
sb_0__2_/mem_right_track_0/sky130_fd_sc_hd__dfxbp_1_1_/CLK 0.347 0.000 -- 4.898 4.898 rp-+ nominal
---------------------------------------------------------------------------------------------------
****************************************
Report : clock timing
@ -34,7 +34,7 @@ Report : clock timing
-setup
Design : fpga_core
Version: P-2019.03-SP4
Date : Fri Nov 6 22:19:36 2020
Date : Sun Nov 8 18:28:15 2020
****************************************
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
@ -43,8 +43,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
Clock Pin Latency CRP Skew Corner
---------------------------------------------------------------------------------------------------
grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.032 rp-+ nominal
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.020 0.000 0.011 rp-+ nominal
grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.427 rp-+ nominal
grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.026 0.000 0.401 rp-+ nominal
---------------------------------------------------------------------------------------------------
@ -53,8 +53,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi
Clock Pin Latency CRP Skew Corner
---------------------------------------------------------------------------------------------------
sb_1__2_/mem_left_track_33/sky130_fd_sc_hd__dfxbp_1_2_/CLK 5.061 rp-+ nominal
cbx_1__2_/mem_bottom_ipin_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.276 0.000 1.785 rp-+ nominal
cby_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.374 rp-+ nominal
sb_2__0_/mem_top_track_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 0.949 0.000 2.424 rp-+ nominal
---------------------------------------------------------------------------------------------------
Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050)
@ -63,7 +63,7 @@ Report : global timing
-format { narrow }
Design : fpga_core
Version: P-2019.03-SP4
Date : Fri Nov 6 22:19:36 2020
Date : Sun Nov 8 18:28:15 2020
****************************************
No setup violations found.
@ -73,8 +73,8 @@ Hold violations
--------------------------------------------------------------
Total reg->reg in->reg reg->out in->out
--------------------------------------------------------------
WNS -0.632 -0.632 0.000 0.000 0.000
TNS -0.750 -0.750 0.000 0.000 0.000
WNS -1.248 -1.248 0.000 0.000 0.000
TNS -1.390 -1.390 0.000 0.000 0.000
NUM 2 2 0 0 0
--------------------------------------------------------------

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