mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #13 from LNIS-Projects/xt_dev
Misc Updates: Caravel User Project Wrapper, Post-PnR Testbench and STA script
This commit is contained in:
Laboratory for Nano Integrated Systems (LNIS)
GitHub
commit
dbe8c73bdb
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@ -0,0 +1,38 @@
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<?xml version="1.0" ?>
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<fabric_key>
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<region id="0">
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<key id="0" alias="sb_2__2_"/>
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<key id="1" alias="cbx_2__2_"/>
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<key id="2" alias="grid_io_top_top_2__3_"/>
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<key id="3" alias="sb_1__2_"/>
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<key id="4" alias="cbx_1__2_"/>
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<key id="5" alias="grid_io_top_top_1__3_"/>
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<key id="6" alias="sb_0__2_"/>
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<key id="7" alias="cby_0__2_"/>
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<key id="8" alias="grid_io_left_left_0__2_"/>
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<key id="9" alias="grid_clb_1__2_"/>
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<key id="10" alias="cby_1__2_"/>
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<key id="11" alias="grid_clb_2__2_"/>
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<key id="12" alias="cby_2__2_"/>
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<key id="13" alias="grid_io_right_right_3__2_"/>
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<key id="14" alias="sb_2__1_"/>
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<key id="15" alias="cbx_2__1_"/>
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<key id="16" alias="sb_1__1_"/>
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<key id="17" alias="cbx_1__1_"/>
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<key id="18" alias="sb_0__1_"/>
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<key id="19" alias="cby_0__1_"/>
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<key id="20" alias="grid_io_left_left_0__1_"/>
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<key id="21" alias="grid_clb_1__1_"/>
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<key id="22" alias="cby_1__1_"/>
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<key id="23" alias="grid_clb_2__1_"/>
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<key id="24" alias="cby_2__1_"/>
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<key id="25" alias="grid_io_right_right_3__1_"/>
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<key id="26" alias="sb_2__0_"/>
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<key id="27" alias="cbx_2__0_"/>
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<key id="28" alias="grid_io_bottom_bottom_2__0_"/>
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<key id="29" alias="sb_1__0_"/>
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<key id="30" alias="cbx_1__0_"/>
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<key id="31" alias="grid_io_bottom_bottom_1__0_"/>
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<key id="32" alias="sb_0__0_"/>
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</region>
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</fabric_key>
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@ -180,7 +180,6 @@
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="Q_N" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="EMBEDDED_IO" prefix="EMBEDDED_IO" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
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/*
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*-------------------------------------------------------------
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*
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* A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC
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*
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*-------------------------------------------------------------
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*/
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module caravel_fpga_wrapper (
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// Fixed I/O interface from Caravel SoC definition
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// DO NOT CHANGE!!!
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inout vdda1, // User area 1 3.3V supply
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inout vdda2, // User area 2 3.3V supply
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inout vssa1, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V supply
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inout vccd2, // User area 2 1.8v supply
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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// Wishbone Slave ports (WB MI A)
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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// Logic Analyzer Signals
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input [127:0] la_data_in,
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output [127:0] la_data_out,
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input [127:0] la_oen,
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// IOs
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input [`MPRJ_IO_PADS-1:0] io_in,
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output [`MPRJ_IO_PADS-1:0] io_out,
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output [`MPRJ_IO_PADS-1:0] io_oeb
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);
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wire [`MPRJ_IO_PADS-1:0] io_in;
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wire [`MPRJ_IO_PADS-1:0] io_out;
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wire [`MPRJ_IO_PADS-1:0] io_oeb;
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// FPGA wires
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wire prog_clk;
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wire Test_en;
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wire clk;
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wire [0:107] gfpga_pad_EMBEDDED_IO_SOC_IN;
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wire [0:107] gfpga_pad_EMBEDDED_IO_SOC_OUT;
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wire [0:107] gfpga_pad_EMBEDDED_IO_SOC_DIR;
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wire ccff_head;
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wire ccff_tail;
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wire sc_head;
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wire sc_tail;
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// Wire-bond TOP side I/O of FPGA to LEFT-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = io_in[24];
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assign io_out[24] = gfpga_pad_EMBEDDED_IO_SOC_OUT[0];
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assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_SOC_DIR[0];
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// Wire-bond TOP side I/O of FPGA to TOP-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[1:9] = io_in[23:15];
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assign io_out[23:15] = gfpga_pad_EMBEDDED_IO_SOC_OUT[1:9];
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assign io_oeb[23:15] = gfpga_pad_EMBEDDED_IO_SOC_DIR[1:9];
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// Wire-bond TOP side I/O of FPGA to RIGHT-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[10:11] = io_in[14:13];
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assign io_out[14:13] = gfpga_pad_EMBEDDED_IO_SOC_OUT[10:11];
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assign io_oeb[14:13] = gfpga_pad_EMBEDDED_IO_SOC_DIR[10:11];
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// Wire-bond RIGHT side I/O of FPGA to RIGHT-side of Caravel interface
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assign ccff_head = io_in[12];
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assign io_out[12] = 1'b0;
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assign io_oeb[12] = 1'b1;
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assign io_out[12] = sc_tail;
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assign io_oeb[12] = 1'b0;
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[12:21] = io_in[10:1];
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assign io_out[10:1] = gfpga_pad_EMBEDDED_IO_SOC_OUT[12:21];
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assign io_oeb[10:1] = gfpga_pad_EMBEDDED_IO_SOC_DIR[12:21];
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assign Test_en = io_in[0];
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assign io_out[0] = 1'b0;
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assign io_oeb[0] = 1'b1;
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// Wire-bond RIGHT side I/O of FPGA to BOTTOm-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[22:23] = la_data_in[0:1];
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assign la_data_in[0:1] = gfpga_pad_EMBEDDED_IO_SOC_OUT[22:23];
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assign la_data_in[0:1] = gfpga_pad_EMBEDDED_IO_SOC_DIR[22:23];
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// Wire-bond BOTTOM side I/O of FPGA to BOTTOM-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[24:95] = la_data_in[2:73];
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assign la_data_in[2:73] = gfpga_pad_EMBEDDED_IO_SOC_OUT[24:95];
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assign la_data_in[2:73] = gfpga_pad_EMBEDDED_IO_SOC_DIR[24:95];
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// Wire-bond LEFT side I/O of FPGA to BOTTOM-side of Caravel interface
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[96:98] = la_data_in[74:76];
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assign la_data_in[74:76] = gfpga_pad_EMBEDDED_IO_SOC_OUT[96:98];
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assign la_data_in[74:76] = gfpga_pad_EMBEDDED_IO_SOC_DIR[96:98];
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// Wire-bond LEFT side I/O of FPGA to LEFT-side of Caravel interface
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assign prog_clk = io_in[37];
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assign io_out[37] = 1'b0;
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assign io_oeb[37] = 1'b1;
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assign clk = io_in[36];
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assign io_out[36] = 1'b0;
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assign io_oeb[36] = 1'b1;
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assign io_out[35] = ccff_tail;
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assign io_oeb[35] = 1'b0;
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assign gfpga_pad_EMBEDDED_IO_SOC_IN[99:107] = io_in[34:26];
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assign io_out[34:26] = gfpga_pad_EMBEDDED_IO_SOC_OUT[99:107];
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assign io_oeb[34:26] = gfpga_pad_EMBEDDED_IO_SOC_DIR[99:107];
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assign sc_in = io_in[25];
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assign io_out[25] = 1'b0;
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assign io_oeb[25] = 1'b1;
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// TODO: Connect spypad from FPGA to logic analyzer ports
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fpga_core fpga_core(.prog_clk(prog_clk),
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.Test_en(Test_en),
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.clk(clk),
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.gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN),
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.gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT),
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.gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR),
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.ccff_head(ccff_head),
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.ccff_tail(ccff_tail),
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.sc_head(sc_head),
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.sc_tail(sc_tail)
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);
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endmodule
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@ -0,0 +1,48 @@
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# This script is designed to generate fabric Verilog netlists
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# with a fixed device layout
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# It will only output netlists to be used by backend tools,
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# i.e., Synopsys ICC2, including
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# - Verilog netlists
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# - fabric hierarchy description for ICC2's hierarchical flow
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# - Timing/Design constraints
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#
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
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# Write the fabric hierarchy of module graph to a file
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# This is used by hierarchical PnR flows
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write_fabric_hierarchy --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/fabric_hierarchy.txt --depth 1
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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# which is required by Synopsys ICC2 parser
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write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC \
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--explicit_port_mapping \
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--verbose
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR}
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -0,0 +1,37 @@
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# This script is designed to generate fabric Verilog netlists
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# with a fixed device layout
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# It will only output netlists to be used by backend tools,
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# i.e., Synopsys ICC2, including
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# - Verilog netlists
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# - fabric hierarchy description for ICC2's hierarchical flow
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# - Timing/Design constraints
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#
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR}
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -0,0 +1,71 @@
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# This script is designed to generate Verilog testbenches
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# with a fixed device layout
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# It will only output netlists to be used by verification tools
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# including
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# - Verilog testbenches, used by ModelSim
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# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
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#
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to clustering nets based on routing results
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pb_pin_fixup --verbose
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
|
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# - Enabled compression on routing architecture modules
|
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
|
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --write_file arch_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write fabric-dependent bitstream
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write_fabric_bitstream --file fabric_bitstream.xml --format xml
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# Write the Verilog testbench for FPGA fabric
|
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# - We suggest the use of same output directory as fabric Verilog netlists
|
||||
# - Must specify the reference benchmark file if you want to output any testbenches
|
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# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench \
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--fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} \
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--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
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--print_top_testbench \
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--print_preconfig_top_testbench \
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--print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
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--explicit_port_mapping
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# Write the SDC to run timing analysis for a mapped FPGA fabric
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write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis
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# Finish and exit OpenFPGA
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exit
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||||
# Note :
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
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|
@ -16,13 +16,14 @@ timeout_each_job = 1*60
|
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga
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openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
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openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=2x2
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openfpga_vpr_route_chan_width=40
|
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openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc
|
||||
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc
|
||||
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||
|
|
|
|||
|
|
@ -16,12 +16,13 @@ timeout_each_job = 1*60
|
|||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga
|
||||
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
|
||||
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=2x2
|
||||
openfpga_vpr_route_chan_width=40
|
||||
openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc
|
||||
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||
|
|
|
|||
|
|
@ -16,13 +16,14 @@ timeout_each_job = 1*60
|
|||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga
|
||||
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
|
||||
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=2x2
|
||||
openfpga_vpr_route_chan_width=40
|
||||
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc
|
||||
openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v
|
||||
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
# Directory to keep all the SDF files for FPGA fabrics
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
#####################################################################
|
||||
# A template script to generate SDF file from post-PnR results
|
||||
# using Synopsys PrimeTime
|
||||
#####################################################################
|
||||
|
||||
##################################
|
||||
# Define environment variables
|
||||
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
|
||||
set FPGA_NETLIST_HOME "../../FPGA1212_FC_HD_SKY_PNR/fpga_core";
|
||||
set SDF_HOME "../../SDF"
|
||||
#
|
||||
# Enable reporting ALL the timing paths even those are NOT constrained
|
||||
set_app_var svr_enable_vpp true
|
||||
|
||||
set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/skywater130_fd_sc_hd/db_nldm"
|
||||
|
||||
set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
|
||||
|
||||
# Top-level module name
|
||||
set DESIGN_NAME fpga_core;
|
||||
|
||||
set FPGA_NETLIST_FILES "fpga_core_icv_in_design.pt.v"
|
||||
|
||||
##################################
|
||||
# Read timing libraries
|
||||
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
|
||||
|
||||
##################################
|
||||
# Read post-PnR netlists
|
||||
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
|
||||
link_design ${DESIGN_NAME}
|
||||
|
||||
##################################
|
||||
# Read post-PnR parasitics
|
||||
read_parasitics ${FPGA_NETLIST_HOME}/fpga_core_icv_in_design.nominal_25.spef
|
||||
|
||||
##################################
|
||||
# Write sdf file
|
||||
write_sdf -version 3.0 ${SDF_HOME}/FPGA1212_FC_HD_SKY_PNR/fpga_core_icv_in_design.pt.sdf
|
||||
|
||||
##################################
|
||||
# Finish and quit
|
||||
# Comment it out if you want to debug
|
||||
#exit
|
||||
|
|
@ -0,0 +1 @@
|
|||
## This directory is where you should run PrimeTime
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,54 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Netlist Summary
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
// Date: Fri Nov 6 11:46:12 2020
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ------ Include preprocessing flags -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/define_simulation.v"
|
||||
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||
|
||||
// ------ Include Skywater cell netlists -----
|
||||
// Cells already used pre-PnR
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v"
|
||||
|
||||
// Cells added due to their use in PnR
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v"
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "and2_output_verilog.v"
|
||||
`endif
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v"
|
||||
`endif
|
||||
Loading…
Reference in New Issue