diff --git a/ARCH/fabric_key/fabric_key_2x2.xml b/ARCH/fabric_key/fabric_key_2x2.xml new file mode 100644 index 0000000..47f4507 --- /dev/null +++ b/ARCH/fabric_key/fabric_key_2x2.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 067356e..30549c4 100644 --- a/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -180,7 +180,6 @@ - diff --git a/HDL/common/caravel_fpga_wrapper.v b/HDL/common/caravel_fpga_wrapper.v new file mode 100644 index 0000000..a3f8719 --- /dev/null +++ b/HDL/common/caravel_fpga_wrapper.v @@ -0,0 +1,140 @@ +/* + *------------------------------------------------------------- + * + * A wrapper for the FPGA IP to fit the I/O interface of Caravel SoC + * + *------------------------------------------------------------- + */ + +module caravel_fpga_wrapper ( + // Fixed I/O interface from Caravel SoC definition + // DO NOT CHANGE!!! + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground + + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oen, + + // IOs + input [`MPRJ_IO_PADS-1:0] io_in, + output [`MPRJ_IO_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-1:0] io_oeb +); + + wire [`MPRJ_IO_PADS-1:0] io_in; + wire [`MPRJ_IO_PADS-1:0] io_out; + wire [`MPRJ_IO_PADS-1:0] io_oeb; + + // FPGA wires + wire prog_clk; + wire Test_en; + wire clk; + wire [0:107] gfpga_pad_EMBEDDED_IO_SOC_IN; + wire [0:107] gfpga_pad_EMBEDDED_IO_SOC_OUT; + wire [0:107] gfpga_pad_EMBEDDED_IO_SOC_DIR; + wire ccff_head; + wire ccff_tail; + wire sc_head; + wire sc_tail; + + // Wire-bond TOP side I/O of FPGA to LEFT-side of Caravel interface + assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = io_in[24]; + assign io_out[24] = gfpga_pad_EMBEDDED_IO_SOC_OUT[0]; + assign io_oeb[24] = gfpga_pad_EMBEDDED_IO_SOC_DIR[0]; + + // Wire-bond TOP side I/O of FPGA to TOP-side of Caravel interface + assign gfpga_pad_EMBEDDED_IO_SOC_IN[1:9] = io_in[23:15]; + assign io_out[23:15] = gfpga_pad_EMBEDDED_IO_SOC_OUT[1:9]; + assign io_oeb[23:15] = gfpga_pad_EMBEDDED_IO_SOC_DIR[1:9]; + + // Wire-bond TOP side I/O of FPGA to RIGHT-side of Caravel interface + assign gfpga_pad_EMBEDDED_IO_SOC_IN[10:11] = io_in[14:13]; + assign io_out[14:13] = gfpga_pad_EMBEDDED_IO_SOC_OUT[10:11]; + assign io_oeb[14:13] = gfpga_pad_EMBEDDED_IO_SOC_DIR[10:11]; + + // Wire-bond RIGHT side I/O of FPGA to RIGHT-side of Caravel interface + assign ccff_head = io_in[12]; + assign io_out[12] = 1'b0; + assign io_oeb[12] = 1'b1; + + assign io_out[12] = sc_tail; + assign io_oeb[12] = 1'b0; + + assign gfpga_pad_EMBEDDED_IO_SOC_IN[12:21] = io_in[10:1]; + assign io_out[10:1] = gfpga_pad_EMBEDDED_IO_SOC_OUT[12:21]; + assign io_oeb[10:1] = gfpga_pad_EMBEDDED_IO_SOC_DIR[12:21]; + + assign Test_en = io_in[0]; + assign io_out[0] = 1'b0; + assign io_oeb[0] = 1'b1; + + // Wire-bond RIGHT side I/O of FPGA to BOTTOm-side of Caravel interface + assign gfpga_pad_EMBEDDED_IO_SOC_IN[22:23] = la_data_in[0:1]; + assign la_data_in[0:1] = gfpga_pad_EMBEDDED_IO_SOC_OUT[22:23]; + assign la_data_in[0:1] = gfpga_pad_EMBEDDED_IO_SOC_DIR[22:23]; + + // Wire-bond BOTTOM side I/O of FPGA to BOTTOM-side of Caravel interface + assign gfpga_pad_EMBEDDED_IO_SOC_IN[24:95] = la_data_in[2:73]; + assign la_data_in[2:73] = gfpga_pad_EMBEDDED_IO_SOC_OUT[24:95]; + assign la_data_in[2:73] = gfpga_pad_EMBEDDED_IO_SOC_DIR[24:95]; + + // Wire-bond LEFT side I/O of FPGA to BOTTOM-side of Caravel interface + assign gfpga_pad_EMBEDDED_IO_SOC_IN[96:98] = la_data_in[74:76]; + assign la_data_in[74:76] = gfpga_pad_EMBEDDED_IO_SOC_OUT[96:98]; + assign la_data_in[74:76] = gfpga_pad_EMBEDDED_IO_SOC_DIR[96:98]; + + // Wire-bond LEFT side I/O of FPGA to LEFT-side of Caravel interface + assign prog_clk = io_in[37]; + assign io_out[37] = 1'b0; + assign io_oeb[37] = 1'b1; + + assign clk = io_in[36]; + assign io_out[36] = 1'b0; + assign io_oeb[36] = 1'b1; + + assign io_out[35] = ccff_tail; + assign io_oeb[35] = 1'b0; + + assign gfpga_pad_EMBEDDED_IO_SOC_IN[99:107] = io_in[34:26]; + assign io_out[34:26] = gfpga_pad_EMBEDDED_IO_SOC_OUT[99:107]; + assign io_oeb[34:26] = gfpga_pad_EMBEDDED_IO_SOC_DIR[99:107]; + + assign sc_in = io_in[25]; + assign io_out[25] = 1'b0; + assign io_oeb[25] = 1'b1; + + // TODO: Connect spypad from FPGA to logic analyzer ports + + fpga_core fpga_core(.prog_clk(prog_clk), + .Test_en(Test_en), + .clk(clk), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR), + .ccff_head(ccff_head), + .ccff_tail(ccff_tail), + .sc_head(sc_head), + .sc_tail(sc_tail) + ); + +endmodule diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga new file mode 100644 index 0000000..971796f --- /dev/null +++ b/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga @@ -0,0 +1,48 @@ +# This script is designed to generate fabric Verilog netlists +# with a fixed device layout +# It will only output netlists to be used by backend tools, +# i.e., Synopsys ICC2, including +# - Verilog netlists +# - fabric hierarchy description for ICC2's hierarchical flow +# - Timing/Design constraints +# +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/fabric_hierarchy.txt --depth 1 + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +# which is required by Synopsys ICC2 parser +write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC \ + --explicit_port_mapping \ + --verbose + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR} + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga new file mode 100644 index 0000000..2371794 --- /dev/null +++ b/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga @@ -0,0 +1,37 @@ +# This script is designed to generate fabric Verilog netlists +# with a fixed device layout +# It will only output netlists to be used by backend tools, +# i.e., Synopsys ICC2, including +# - Verilog netlists +# - fabric hierarchy description for ICC2's hierarchical flow +# - Timing/Design constraints +# +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR} + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga new file mode 100644 index 0000000..ecd657d --- /dev/null +++ b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga @@ -0,0 +1,71 @@ +# This script is designed to generate Verilog testbenches +# with a fixed device layout +# It will only output netlists to be used by verification tools +# including +# - Verilog testbenches, used by ModelSim +# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime +# +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file arch_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench \ + --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} \ + --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ + --print_top_testbench \ + --print_preconfig_top_testbench \ + --print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \ + --explicit_port_mapping + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf index 2d690ad..a172e5d 100644 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf @@ -16,13 +16,14 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_example_script.openfpga +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf index 86a19dd..c017e78 100644 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf @@ -16,12 +16,13 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_example_script.openfpga +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml diff --git a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf index 58349ae..55cb178 100644 --- a/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_non_adder_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf @@ -16,13 +16,14 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_example_script.openfpga +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=40 openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/SRC/fabric_netlists.v +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_2x2.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml diff --git a/SDF/README.md b/SDF/README.md new file mode 100644 index 0000000..1f03d41 --- /dev/null +++ b/SDF/README.md @@ -0,0 +1 @@ +# Directory to keep all the SDF files for FPGA fabrics diff --git a/SNPS_PT/SCRIPT/generate_sdf.tcl b/SNPS_PT/SCRIPT/generate_sdf.tcl new file mode 100644 index 0000000..e9a605e --- /dev/null +++ b/SNPS_PT/SCRIPT/generate_sdf.tcl @@ -0,0 +1,44 @@ +##################################################################### +# A template script to generate SDF file from post-PnR results +# using Synopsys PrimeTime +##################################################################### + +################################## +# Define environment variables +set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; +set FPGA_NETLIST_HOME "../../FPGA1212_FC_HD_SKY_PNR/fpga_core"; +set SDF_HOME "../../SDF" +# +# Enable reporting ALL the timing paths even those are NOT constrained +set_app_var svr_enable_vpp true + +set search_path ". * ${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/skywater130_fd_sc_hd/db_nldm" + +set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db" + +# Top-level module name +set DESIGN_NAME fpga_core; + +set FPGA_NETLIST_FILES "fpga_core_icv_in_design.pt.v" + +################################## +# Read timing libraries +read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" + +################################## +# Read post-PnR netlists +read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES} +link_design ${DESIGN_NAME} + +################################## +# Read post-PnR parasitics +read_parasitics ${FPGA_NETLIST_HOME}/fpga_core_icv_in_design.nominal_25.spef + +################################## +# Write sdf file +write_sdf -version 3.0 ${SDF_HOME}/FPGA1212_FC_HD_SKY_PNR/fpga_core_icv_in_design.pt.sdf + +################################## +# Finish and quit +# Comment it out if you want to debug +#exit diff --git a/SNPS_PT/TMP/README.md b/SNPS_PT/TMP/README.md new file mode 100644 index 0000000..f2433d4 --- /dev/null +++ b/SNPS_PT/TMP/README.md @@ -0,0 +1 @@ +## This directory is where you should run PrimeTime diff --git a/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v b/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v new file mode 100644 index 0000000..8aad041 --- /dev/null +++ b/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v @@ -0,0 +1,2411 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: FPGA Verilog Testbench for Top-level netlist of Design: and2 +// Author: Xifan TANG +// Organization: University of Utah +// Date: Sun Nov 8 11:48:41 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +module and2_autocheck_top_tb; +// ----- Local wires for global ports of FPGA fabric ----- +wire [0:0] prog_clk; +wire [0:0] Test_en; +wire [0:0] clk; + +// ----- Local wires for I/Os of FPGA fabric ----- + +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN; + +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT; +wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR; + +reg [0:0] config_done; +wire [0:0] prog_clock; +reg [0:0] prog_clock_reg; +wire [0:0] op_clock; +reg [0:0] op_clock_reg; +reg [0:0] prog_reset; +reg [0:0] prog_set; +reg [0:0] greset; +reg [0:0] gset; +// ---- Configuration-chain head ----- +reg [0:0] ccff_head; +// ---- Configuration-chain tail ----- +wire [0:0] ccff_tail; + +// ---- Scan-chain head ----- +wire [0:0] sc_head; +// ---- Scan-chain tail ----- +wire [0:0] sc_tail; + +// ----- Shared inputs ------- + reg [0:0] a; + reg [0:0] b; + +// ----- FPGA fabric outputs ------- + wire [0:0] out_c_fpga; + +`ifdef AUTOCHECKED_SIMULATION + +// ----- Benchmark outputs ------- + wire [0:0] out_c_benchmark; + +// ----- Output vectors checking flags ------- + reg [0:0] out_c_flag; + +`endif + +// ----- Error counter: Deposit an error for config_done signal is not raised at the beginning ----- + integer nb_error= 1; +// ----- Number of clock cycles in configuration phase: 2107 ----- +// ----- Begin configuration done signal generation ----- +initial + begin + config_done[0] = 1'b0; + end + +// ----- End configuration done signal generation ----- + +// ----- Begin raw programming clock signal generation ----- +initial + begin + prog_clock_reg[0] = 1'b0; + end +always + begin + #5 prog_clock_reg[0] = ~prog_clock_reg[0]; + end + +// ----- End raw programming clock signal generation ----- + +// ----- Actual programming clock is triggered only when config_done and prog_reset are disabled ----- + assign prog_clock[0] = prog_clock_reg[0] & (~config_done[0]) & (~prog_reset[0]); + +// ----- Begin raw operating clock signal generation ----- +initial + begin + op_clock_reg[0] = 1'b0; + end +always wait(~greset) + begin + #0.5203860402 op_clock_reg[0] = ~op_clock_reg[0]; + end + +// ----- End raw operating clock signal generation ----- +// ----- Actual operating clock is triggered only when config_done is enabled ----- + assign op_clock[0] = op_clock_reg[0] & config_done[0]; + +// ----- Begin programming reset signal generation ----- +initial + begin + prog_reset[0] = 1'b1; + #10 prog_reset[0] = 1'b0; + end + +// ----- End programming reset signal generation ----- + +// ----- Begin programming set signal generation ----- +initial + begin + prog_set[0] = 1'b1; + #10 prog_set[0] = 1'b0; + end + +// ----- End programming set signal generation ----- + +// ----- Begin operating reset signal generation ----- +// ----- Reset signal is enabled until the first clock cycle in operation phase ----- +initial + begin + greset[0] = 1'b1; + wait(config_done) + #1.04077208 greset[0] = 1'b1; + #2.081544161 greset[0] = 1'b0; + end + +// ----- End operating reset signal generation ----- +// ----- Begin operating set signal generation: always disabled ----- +initial + begin + gset[0] = 1'b0; + end + +// ----- End operating set signal generation: always disabled ----- + +// ----- Begin connecting global ports of FPGA fabric to stimuli ----- + assign clk[0] = op_clock[0]; + assign prog_clk[0] = prog_clock[0]; + assign Test_en[0] = 1'b0; + assign sc_head[0] = 1'b0; + +// ----- End connecting global ports of FPGA fabric to stimuli ----- +// ----- FPGA top-level module to be capsulated ----- + fpga_core FPGA_DUT ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:17]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:17]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:17]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail[0]), + .sc_head(sc_head[0]), + .sc_tail(sc_tail[0]) + ); + +// ----- Link BLIF Benchmark I/Os to FPGA I/Os ----- +// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[16] ----- + assign gfpga_pad_EMBEDDED_IO_SOC_IN[16] = a[0]; + +// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_IN[6] ----- + assign gfpga_pad_EMBEDDED_IO_SOC_IN[6] = b[0]; + +// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_EMBEDDED_IO_SOC_OUT[9] ----- + assign out_c_fpga[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[9]; + +// ----- Wire unused FPGA I/Os to constants ----- + assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[9] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_IN[17] = 1'b0; + + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[1] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[2] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[3] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[4] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[5] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[6] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[7] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[8] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[10] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[11] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[12] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[13] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[14] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[15] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[16] = 1'b0; + assign gfpga_pad_EMBEDDED_IO_SOC_OUT[17] = 1'b0; + +`ifdef AUTOCHECKED_SIMULATION +// ----- Reference Benchmark Instanication ------- + and2 REF_DUT( + .a(a), + .b(b), + .c(out_c_benchmark) ); +// ----- End reference Benchmark Instanication ------- + +`endif + + +// ----- Task: input values during a programming clock cycle ----- +task prog_cycle_task; +input [0:0] ccff_head_val; + begin + @(negedge prog_clock[0]); + ccff_head[0] = ccff_head_val[0]; + end +endtask + +// ----- Begin bitstream loading during configuration phase ----- +initial + begin +// ----- Configuration chain default input ----- + ccff_head[0] = 1'b0; + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + 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prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + @(negedge prog_clock[0]); + config_done[0] <= 1'b1; + end +// ----- End bitstream loading during configuration phase ----- +// ----- Input Initialization ------- + initial begin + a <= 1'b0; + b <= 1'b0; + + out_c_flag[0] <= 1'b0; + end + +// ----- Input Stimulus ------- + always@(negedge op_clock[0]) begin + a <= $random; + b <= $random; + end + +`ifdef AUTOCHECKED_SIMULATION +// ----- Begin checking output vectors ------- +// ----- Skip the first falling edge of clock, it is for initialization ------- + reg [0:0] sim_start; + + always@(negedge op_clock[0]) begin + if (1'b1 == sim_start[0]) begin + sim_start[0] <= ~sim_start[0]; + end else begin + if(!(out_c_fpga === out_c_benchmark) && !(out_c_benchmark === 1'bx)) begin + out_c_flag <= 1'b1; + end else begin + out_c_flag<= 1'b0; + end + end + end + + always@(posedge out_c_flag) begin + if(out_c_flag) begin + nb_error = nb_error + 1; + $display("Mismatch on out_c_fpga at time = %t", $realtime); + end + end + +`endif + +`ifdef AUTOCHECKED_SIMULATION +// ----- Configuration done must be raised in the end ------- + always@(posedge config_done[0]) begin + nb_error = nb_error - 1; + end +`endif + +`ifdef ICARUS_SIMULATOR +// ----- Begin Icarus requirement ------- + initial begin + $dumpfile("and2_formal.vcd"); + $dumpvars(1, and2_autocheck_top_tb); + end +`endif +// ----- END Icarus requirement ------- + +initial begin + sim_start[0] <= 1'b1; + $timeformat(-9, 2, "ns", 20); + $display("Simulation start"); +// ----- Can be changed by the user for his/her need ------- + #21097 + if(nb_error == 0) begin + $display("Simulation Succeed"); + end else begin + $display("Simulation Failed with %d error(s)", nb_error); + end + $finish; +end + +endmodule +// ----- END Verilog module for and2_autocheck_top_tb ----- + diff --git a/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v new file mode 100644 index 0000000..6903652 --- /dev/null +++ b/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_include_netlists.v @@ -0,0 +1,54 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Fri Nov 6 11:46:12 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include preprocessing flags ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +// Cells already used pre-PnR +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v" + +// Cells added due to their use in PnR +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" +`endif