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[HDL] Add embedded I/O HDL wrapper using the high density cells

This commit is contained in:
tangxifan 2020-11-03 09:05:20 -07:00
parent 0958d9c50f
commit b67896a225
1 changed files with 26 additions and 11 deletions
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37
PDK/sc_verilog/std_cell_extract.v
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@ -1,16 +1,5 @@
`timescale 1ns/1ps
//
//
//
//
//
//
//
//
//
module GPIO (A, IE, OE, Y, in, out, mem_out);
output A;
output IE;
@ -27,3 +16,29 @@ module GPIO (A, IE, OE, Y, in, out, mem_out);
.A (mem_out),
.Y (OE) );
endmodule
//-----------------------------------------------------
// Function : A minimum input pad
//-----------------------------------------------------
module GPIN (
inout A, // External PAD signal
output Y // Data input
);
// Assume a 4x buf is enough to drive the global routing
sky130_fd_sc_hd__buf_4 in_buf (
.A (A),
.X (Y) );
endmodule
//-----------------------------------------------------
// Function : A minimum output pad
//-----------------------------------------------------
module GPOUT (
inout Y, // External PAD signal
input A // Data output
);
// Assume a 4x buf is enough to drive the block outside FPGA
sky130_fd_sc_hd__buf_4 in_buf (
.A (A),
.X (Y) );
endmodule