diff --git a/PDK/sc_verilog/std_cell_extract.v b/PDK/sc_verilog/std_cell_extract.v
index be56f7f..5267d22 100644
--- a/PDK/sc_verilog/std_cell_extract.v
+++ b/PDK/sc_verilog/std_cell_extract.v
@@ -1,16 +1,5 @@
 `timescale 1ns/1ps
 
-//
-//
-//
-//
-//
-//
-
-//
-//
-//
-
 module GPIO (A, IE, OE, Y, in, out, mem_out);
     output A;
     output IE;
@@ -27,3 +16,29 @@ module GPIO (A, IE, OE, Y, in, out, mem_out);
         .A	(mem_out),
         .Y	(OE) );
 endmodule
+
+//-----------------------------------------------------
+// Function    : A minimum input pad
+//-----------------------------------------------------
+module GPIN (
+  inout A, // External PAD signal
+  output Y // Data input
+);
+  // Assume a 4x buf is enough to drive the global routing
+  sky130_fd_sc_hd__buf_4 in_buf (
+        .A	(A),
+        .X	(Y) );
+endmodule
+
+//-----------------------------------------------------
+// Function    : A minimum output pad
+//-----------------------------------------------------
+module GPOUT (
+  inout Y, // External PAD signal
+  input A // Data output
+);
+  // Assume a 4x buf is enough to drive the block outside FPGA
+  sky130_fd_sc_hd__buf_4 in_buf (
+        .A	(A),
+        .X	(Y) );
+endmodule