tangxifan
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e71b5eb3f4
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[Git] add OpenFPGA as a submodule
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2020-11-30 18:25:11 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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f4397e1656
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Merge pull request #47 from LNIS-Projects/xt_dev
Bug fix in the arch port naming
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2020-11-30 18:23:38 -07:00 |
tangxifan
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be9399a016
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[Arch] Bug fix in the arch port naming: prog_reset is a reserved word in OpenFPGA
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2020-11-30 17:58:56 -07:00 |
tangxifan
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c1db942cc6
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Merge pull request #46 from LNIS-Projects/tpagarani_dev
modify carry chain to change output mux
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2020-11-30 13:57:56 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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0c5b378592
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Merge pull request #45 from LNIS-Projects/xt_dev
Wrapper Testbench Converter
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2020-11-30 11:44:00 -07:00 |
tangxifan
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c676db1fe4
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[Testbench] Bug fix in the ccff post-pnr testbench template
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2020-11-30 11:18:42 -07:00 |
tangxifan
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c638edfc14
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[Testbench] Regenerate ccff/scff testbenches for wrapper
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2020-11-30 10:33:50 -07:00 |
tangxifan
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a900cba5a5
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[HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail
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2020-11-30 10:29:05 -07:00 |
tangxifan
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e63cb7ca89
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[Testbench] Rename testbench top module to be compatible with verification scripts
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2020-11-30 10:23:30 -07:00 |
tangxifan
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c70d5ac4f0
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[Testbench] Add ccff test wrapper testbench and include netlist
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2020-11-30 09:42:31 -07:00 |
tangxifan
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2b40d5fb4b
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[HDL] Bug fix
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2020-11-30 09:34:26 -07:00 |
Tarachand Pagarani
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9f7fb8a34d
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modify carry chain to change output mux
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2020-11-30 07:08:09 -08:00 |
tangxifan
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fc3eadaf29
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[Testbench] Add SCFF test for wrapper
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2020-11-29 22:58:48 -07:00 |
tangxifan
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0bf5a400e8
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[Testbench] Add include netlists for wrapper testbenches
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2020-11-29 22:48:25 -07:00 |
tangxifan
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0ccc18d848
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[Testbench] Bug fix in the paths to generate wrapper testbenches
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2020-11-29 22:48:01 -07:00 |
tangxifan
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931b93b83d
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[Testbench] Now wrapper testbench conversion can be batched
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2020-11-29 22:38:16 -07:00 |
tangxifan
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12c3e157bf
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[Testbench] Add a tempo fix on the analog pins
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2020-11-29 22:32:36 -07:00 |
tangxifan
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50089e11f9
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[Testbench] Bug fix
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2020-11-29 22:20:15 -07:00 |
tangxifan
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4b681b88a6
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[Testbench] Fix the unconnected wbs_we_i pin
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2020-11-29 22:17:10 -07:00 |
tangxifan
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724696a661
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[Testbench] Add missing ports in the wrapper
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2020-11-29 22:16:04 -07:00 |
tangxifan
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5235424e83
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[Testbench] Adapt path for signal init in testbench converter
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2020-11-29 21:44:29 -07:00 |
tangxifan
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fec19ebc55
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[Testbench] Typo fix
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2020-11-29 21:19:56 -07:00 |
tangxifan
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951f5f84ee
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[Testbench] Typo fix
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2020-11-29 21:15:36 -07:00 |
tangxifan
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78addbe294
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[HDL] Name fix to be compatible with testbench generation
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2020-11-29 21:01:44 -07:00 |
tangxifan
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e3efcebf2b
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[Testbench] Bug fix in include netlist
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2020-11-29 21:00:20 -07:00 |
tangxifan
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4ab69d925c
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[Testbench] Add include netlist for wrapper testbench
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2020-11-29 20:46:50 -07:00 |
tangxifan
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eeb904a3e3
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[Testbench] Typo fix in wrapper testbench converter
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2020-11-29 20:32:59 -07:00 |
tangxifan
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a414a600a6
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[Testbench] Bug fixed in wrapper testbench generator
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2020-11-29 20:31:19 -07:00 |
tangxifan
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64ae33066e
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[Testbench] Add script to convert post-PnR testbench for wrapper testbench
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2020-11-29 20:23:34 -07:00 |
tangxifan
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fcee5f1c91
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[HDL] Typo fix in pin assignment description
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2020-11-29 18:02:26 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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b0b5b0b325
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Merge pull request #44 from LNIS-Projects/xt_dev
Upgraded Caravel Wrapper Generator
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2020-11-29 13:27:52 -07:00 |
tangxifan
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de5411db6b
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[HDL] Add pin assignement for v1.1 HD FPGA
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2020-11-29 12:58:53 -07:00 |
tangxifan
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cdfa3d5ff4
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[HDL] Update wrapper using the new generator
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2020-11-29 12:47:52 -07:00 |
tangxifan
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d0f9ca718d
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[HDL] bug fix in wrapper line generator
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2020-11-29 12:47:22 -07:00 |
tangxifan
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9f82d9bf54
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[HDL] Correct typo in wrapper generator
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2020-11-29 12:39:56 -07:00 |
tangxifan
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899018d503
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[HDL] Bug fix in wrapper template
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2020-11-29 12:38:25 -07:00 |
tangxifan
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ea758cd5b1
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[HDL] Update wrapper template as most codes can be auto-generated
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2020-11-29 12:36:23 -07:00 |
tangxifan
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f78a53fd03
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[HDL] Add tab to wrapper line generation
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2020-11-29 12:35:24 -07:00 |
tangxifan
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ebd3053a4e
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[HDL] bug fix in wrapper generator
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2020-11-29 12:31:32 -07:00 |
tangxifan
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0e964534bc
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[HDL] bug fix in wrapper line generator
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2020-11-29 12:01:15 -07:00 |
tangxifan
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9622b44554
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[HDL] Bug fix in JSON file syntax
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2020-11-29 11:59:56 -07:00 |
tangxifan
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27da78fe29
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[HDL] Update wrapper line generator to parse json data
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2020-11-29 11:57:34 -07:00 |
tangxifan
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329b6644f3
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[Script] Bug fix in creating directories for verification task
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2020-11-29 11:02:23 -07:00 |
Ganesh Gore
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20dc203b31
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[FPGA1212_v1] Module level results
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2020-11-29 11:02:17 -07:00 |
Ganesh Gore
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225feaef3c
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[FPGA1212_v1] Added top-level pnr screenshots
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2020-11-29 10:59:15 -07:00 |
tangxifan
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4ec490645d
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Merge branch 'master' of https://github.com/LNIS-Projects/skywater-openfpga into xt_dev
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2020-11-29 10:35:40 -07:00 |
tangxifan
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bc3d839e5b
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[HDL] Upgrading code generator for wrapper
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2020-11-29 10:35:10 -07:00 |
tangxifan
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a50dfc09b5
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Merge pull request #43 from LNIS-Projects/ganesh_dev
[FPGA1212_V1] Updated design
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2020-11-29 10:34:29 -07:00 |
Ganesh Gore
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7db7c240e3
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[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed
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2020-11-29 10:24:03 -07:00 |
tangxifan
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aac8ddc3ec
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[HDL] update json to ease parsing
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2020-11-28 21:10:46 -07:00 |