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Merge pull request #46 from LNIS-Projects/tpagarani_dev 

modify carry chain to change output mux
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tangxifan 2020-11-30 13:57:56 -07:00 committed by GitHub
parent 0c5b378592 9f7fb8a34d
commit c1db942cc6
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2 changed files with 30 additions and 21 deletions
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12
ARCH/openfpga_arch_template/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml
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@ -187,6 +187,16 @@
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="output" prefix="a" lib_name="Y" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/sky130_fd_sc_hd_wrapper.v">
<design_technology type="cmos"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A0" size="1"/>
<port type="input" prefix="b" lib_name="A1" size="1"/>
<port type="input" prefix="cin" lib_name="S" size="1"/>
<port type="output" prefix="cout" lib_name="X" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" num_regions="1"/>
@ -220,7 +230,7 @@
<pb_type name="SUPER_LOGIC_CELL.LC" physical_mode_name="PHYSICAL"/>
<pb_type name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.ff" circuit_model_name="sky130_fd_sc_hd__dfxtp_1"/>
<pb_type name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.co_mux" circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="sky130_fd_sc_hd__mux2_1_wrapper"/>
<!-- BEGIN Binding operating pb_types in mode 'ble4' -->
<pb_type name="SUPER_LOGIC_CELL.LC[DEFAULT].DEFAULT.lut_part[VPR_LUT4].VPR_LUT4.lut_inst" physical_pb_type_name="SUPER_LOGIC_CELL.LC[PHYSICAL].PHYSICAL.frac_logic.frac_lut4" mode_bits="0">
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->

39
ARCH/vpr_arch/ql_ap3_8x8_arch_vpr_routing.xml
View File

@ -27,14 +27,14 @@
<port name="lut4_out"/>
</output_ports>
</model>
<model name="MUX2">
<model name="carry_follower">
<input_ports>
<port name="in0" />
<port name="in1" />
<port name="sel" />
</input_ports>
<port name="a"/>
<port name="b"/>
<port name="cin"/>
</input_ports>
<output_ports>
<port name="out" />
<port name="cout"/>
</output_ports>
</model>
<model name="LUT4">
@ -304,22 +304,21 @@
<output name="lut2_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/>
</pb_type>
<pb_type name="co_mux" blif_model=".subckt MUX2" num_pb="1">
<input name="in0" num_pins="1"/>
<input name="in1" num_pins="1"/>
<input name="sel" num_pins="1"/>
<output name="out" num_pins="1"/>
<pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1">
<input name="a" num_pins="1"/>
<input name="b" num_pins="1"/>
<input name="cin" num_pins="1"/>
<output name="cout" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="direct1" input="frac_logic.LI[0]" output="frac_lut4.in[0]" />
<direct name="direct2" input="frac_logic.LI[1]" output="frac_lut4.in[1]" />
<mux name="i2_ci" input="frac_logic.LI[2] frac_logic.CI" output="frac_lut4.in[2]"/>
<direct name="direct3" input="frac_logic.LI[3]" output="frac_lut4.in[3]" />
<direct name="direct4" input="frac_lut4.lut4_out" output="frac_logic.O" />
<direct name="direct5" input="frac_lut4.lut2_out[1]" output="co_mux.in0" />
<direct name="direct6" input="frac_logic.CI" output="co_mux.in1" />
<direct name="direct7" input="frac_lut4.lut2_out[0]" output="co_mux.sel" />
<direct name="direct8" input="co_mux.out" output="frac_logic.CO" />
<direct name="direct1" input="frac_logic.LI[0:1]" output="frac_lut4.in[0:1]" />
<direct name="direct2" input="frac_logic.LI[3:3]" output="frac_lut4.in[3:3]" />
<direct name="direct3" input="frac_lut4.lut4_out" output="frac_logic.O" />
<direct name="direct4" input="frac_lut4.lut2_out[1:1]" output="carry_follower.a" />
<direct name="direct5" input="frac_logic.CI" output="carry_follower.b" />
<direct name="direct6" input="frac_lut4.lut2_out[0:0]" output="carry_follower.cin" />
<direct name="direct7" input="carry_follower.out" output="frac_logic.CO" />
<mux name="i2_ci" input="frac_logic.LI[2:2] frac_logic.CI" output="frac_lut4.in[2:2]"/>
</interconnect>
</pb_type>
<!-- Define flip-flop with scan-chain capability, DI is the scan-chain data input -->