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SOFA
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532 Commits 16 Branches 1 Tag 1.8 GiB
Commit Graph

58 Commits

Author SHA1 Message Date
tangxifan 9c2764723f [HDL] Update caravel include netlist to use simulation without power pins 2020-12-16 20:26:53 -07:00
tangxifan c0e521ed85 [HDL] Update caravel integration netlist with mpw-b tagged version 2020-12-16 16:41:18 -07:00
tangxifan efe404e62b [Testbench] Remove unnecessary RTL netlist from synthesis 2020-12-16 16:09:06 -07:00
tangxifan 3897c18ebe [HDL] Bug fix in VSS port naming 2020-12-16 13:40:09 -07:00
tangxifan 3b56703c35 [HDL] Add VDD/VSS connects to wrapper netlists 2020-12-16 11:44:40 -07:00
tangxifan 682d15875b [HDL] Add user project wrapper for post-PnRed FPGA netlists so that we can plug in for Caravel RTL simulation 2020-12-16 11:12:28 -07:00
tangxifan edff7f3da0 [HDL] Patch the include netlist with missing HDL netlists from Caravel RTL 2020-12-15 17:58:17 -07:00
tangxifan d663d240cb [HDL] Add include netlist for Caravel RTL netlists 2020-12-15 16:14:01 -07:00
tangxifan 1e490c1714 [HDL] Add digital I/O self testing testbench 2020-12-11 16:11:12 -07:00
tangxifan 52d98eb7ca [HDL] Revert I/O cell back to the current design in GDS 2020-12-11 11:26:46 -07:00
tangxifan c1cdca61b5 [HDL] Critical Patch on the digital I/O cell which now outputs 'Z' when input mode is selected 2020-12-11 10:59:28 -07:00
tangxifan 9c80a1b1a7 [HDL] Bug fix in the custom cell code generator 2020-12-10 15:45:20 -07:00
tangxifan ed92cba451 [HDL] Add netlist for simulation with Caravel + FPGA 2020-12-08 15:35:38 -07:00
tangxifan 7f53e0ef18 [HDL] Add HDL for custom cells 2020-12-06 14:15:03 -07:00
tangxifan aa90424ada [HDL] Add primitive include lines for digital I/O built with HD cells 2020-12-06 11:35:35 -07:00
tangxifan 21a4928002 [HDL] Bug fix in custom cell code generator 2020-12-06 11:28:37 -07:00
tangxifan 22f2b3aa90 [HDL] Add python script to adapt OpenFPGA MUX primitives to use custom cells 2020-12-05 21:14:56 -07:00
tangxifan 4875b2de95 [HDL] Patch pin assignment names to be consistent with post-PnR netlists 2020-12-02 14:02:18 -07:00
Ganesh Gore f385c0ca11 [FPGA1212_v1.1] Added OpenFPGA task and verilog netlist 2020-12-02 01:43:05 -07:00
tangxifan a900cba5a5 [HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail 2020-11-30 10:29:05 -07:00
tangxifan 78addbe294 [HDL] Name fix to be compatible with testbench generation 2020-11-29 21:01:44 -07:00
tangxifan fcee5f1c91 [HDL] Typo fix in pin assignment description 2020-11-29 18:02:26 -07:00
tangxifan de5411db6b [HDL] Add pin assignement for v1.1 HD FPGA 2020-11-29 12:58:53 -07:00
tangxifan cdfa3d5ff4 [HDL] Update wrapper using the new generator 2020-11-29 12:47:52 -07:00
tangxifan d0f9ca718d [HDL] bug fix in wrapper line generator 2020-11-29 12:47:22 -07:00
tangxifan 9f82d9bf54 [HDL] Correct typo in wrapper generator 2020-11-29 12:39:56 -07:00
tangxifan 899018d503 [HDL] Bug fix in wrapper template 2020-11-29 12:38:25 -07:00
tangxifan ea758cd5b1 [HDL] Update wrapper template as most codes can be auto-generated 2020-11-29 12:36:23 -07:00
tangxifan f78a53fd03 [HDL] Add tab to wrapper line generation 2020-11-29 12:35:24 -07:00
tangxifan ebd3053a4e [HDL] bug fix in wrapper generator 2020-11-29 12:31:32 -07:00
tangxifan 0e964534bc [HDL] bug fix in wrapper line generator 2020-11-29 12:01:15 -07:00
tangxifan 9622b44554 [HDL] Bug fix in JSON file syntax 2020-11-29 11:59:56 -07:00
tangxifan 27da78fe29 [HDL] Update wrapper line generator to parse json data 2020-11-29 11:57:34 -07:00
tangxifan bc3d839e5b [HDL] Upgrading code generator for wrapper 2020-11-29 10:35:10 -07:00
tangxifan aac8ddc3ec [HDL] update json to ease parsing 2020-11-28 21:10:46 -07:00
tangxifan 47389a483e [HDL] Add json description for pin assignment v1.0 2020-11-28 20:55:41 -07:00
tangxifan aff43bf473 [Doc] Add README to HDL common files 2020-11-28 17:37:36 -07:00
tangxifan 31dcd4a17f [HDL] Add a wrapper for HD MUX2 cell required by carry logic 2020-11-27 16:01:27 -07:00
tangxifan b08b77994c [HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA 2020-11-20 18:13:37 -07:00
tangxifan 6fa5e935fa [HDL] Update wrapper generator to use tri-state buffer for outputs 2020-11-19 17:14:50 -07:00
tangxifan dde0656968 [HDL] Patch tech mapped netlists of digital I/O and remove the out-of-date behavoiral codes 2020-11-19 16:31:06 -07:00
Ganesh Gore 37e72cffb5 [HDL] Updated wrapper generation script 2020-11-18 23:15:26 -07:00
tangxifan 014a6b56ce [HDL] Add clock switch to wrapper 2020-11-18 20:50:10 -07:00
tangxifan 33824bf179 [HDL] Update caravel wrapper for new I/O assignment 2020-11-18 20:44:54 -07:00
tangxifan ce91890a0e [HDL] Now use a proper drive strength of 4 in the digital I/O cells 2020-11-18 11:58:21 -07:00
tangxifan 4837e6d424 [HDL] Remove out-of-data wrapper 2020-11-18 11:30:53 -07:00
tangxifan a916ce7e03 [HDL] Bug fix in the caravel fpga wrapper built with hd cell library 2020-11-18 11:29:37 -07:00
tangxifan d36cb8abe7 [HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script 2020-11-17 21:44:13 -07:00
tangxifan 58440b8c42 [HDL] Bug fix in I/O cell 2020-11-17 20:03:20 -07:00
tangxifan 8803b30b26 [HDL] Rename por of I/O cell to be consistent with documentation 2020-11-17 19:33:53 -07:00