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633 Commits

Author SHA1 Message Date
Kevin Liao 9318f0e49e Merge remote-tracking branch 'origin' into ql_ccff_dummy_stdcell_pointer 
For PR #91, in order to be merged to master, Xifan advise to merge with master.
 2021-02-03 20:25:50 -08:00
Lalit Narain Sharma c444e17588
Merge pull request #92 from antmicro/k4_N8-phy-primitives-fix 
Models and pb_types annotation for k4_N8 VPR architecture
 2021-02-03 17:01:43 +05:30
Maciej Kurc a6db672595 Fixed incorrect IREG pack-pattern 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-03 11:10:39 +01:00
Maciej Kurc 1e3490dc8d Added port relations to models and timing annotation to pb_types of the k4_N8 VPR architecture. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-03 11:10:39 +01:00
tpagarani 4ea02f257a
Merge pull request #93 from lnis-uofu/ap3_test 
using default yosys script instead of custom script for multi_enc_dec…
 2021-02-03 05:00:48 -05:00
Lalit Sharma 0cdd94139f using default yosys script instead of custom script for multi_enc_decx2x4 design as custom script generated blif file is causing an assertion in openfpga. This is done temporarily to enable developers to checkin in SOFA, also requested Xifan to review this crash in openfpga. 2021-02-03 01:08:27 -08:00
Kevin Liao b5be7692c4 (1)CFG_DONE to add is_config_enable(2)reset default=1 under tile_annotations 2021-01-29 08:56:59 -08:00
tpagarani 61655b8e1e
Merge pull request #90 from lnis-uofu/ql_ccff_dummy_stdcell_pointer 
SOFA branch ql_ccff_dummy_stdcell_pointer
 2021-01-26 23:04:50 -05:00
Kevin Liao 924b3d51de correct dummy stdcell verilog pointer 2021-01-26 15:45:59 -08:00
Kevin Liao 965fbdbfea correct to sky130_fd_sc_hd__sdfrtp_1 2021-01-26 15:36:33 -08:00
Kevin Liao f7feca6686 update header for description 2021-01-26 10:10:35 -08:00
Kevin Liao f0050b851d QuickLogic physical ccff 2021-01-26 09:43:53 -08:00
Kevin Liao 84c217bc56 replace CFGSDFFR with QL_CCFF and fix testbench related 2021-01-26 09:41:23 -08:00
liaokevin-ql d2240d8539
Merge pull request #86 from lnis-uofu/k4_N8_interface 
Merging registered/non-registered related IO definition in k4_N8 device
 2021-01-25 10:38:13 -08:00
Kevin Liao f1eb4c4f88 rename module name to IO from EMBEDDED_IO_HD 2021-01-21 20:52:16 -08:00
Kevin Liao f7af0b40cf rename prefix for circuit_model iopad 2021-01-21 20:50:00 -08:00
Tarachand Pagarani 9c1b2ca4d4 update the name of IO cell and ports to be consistent with QL names 2021-01-21 04:18:25 -08:00
tpagarani 658edb47f7
Merge pull request #89 from lnis-uofu/custom_yosys_scr 
Using custom yosys script for benchmarks run in generate_testbench task
 2021-01-21 06:58:01 -05:00
Lalit Sharma c34c777409 Using custom yosys script for benchmarks run in generate_testbench task 2021-01-20 21:18:38 -08:00
Tarachand Pagarani 3085cf7c2c remove io clk from output mux till prepack in VPR is updated to ignore physical mode 2021-01-20 01:16:59 -08:00
ganeshgore cbb7e020e8
Merge pull request #88 from lnis-uofu/xt_dev 
Minor fix on the waveform display for I/O circuitry
 2021-01-19 22:47:05 -07:00
Tarachand Pagarani 36739d9c7c Merge branch 'k4_N8_interface' of https://github.com/lnis-uofu/SOFA into k4_N8_interface 2021-01-17 23:55:54 -08:00
Tarachand Pagarani 72d8d20356 1. Add 4 clocks to IO interfaces 
2. Mux the clock with the output for sending the clock out of the FPGA
 2021-01-17 23:54:39 -08:00
tangxifan d316f5cf21 Merge branch 'master' into xt_dev 2021-01-15 17:39:52 -07:00
tangxifan 851aa6e07d [Doc] Minor fix on the waveform display for I/O circuitry 2021-01-15 17:08:10 -07:00
Kevin Liao 69ed6b5e27 forgot to add new port, IO_ISOL_N, for EMBEDDED_IO_HD 2021-01-15 12:48:32 -08:00
Kevin Liao f428234df8 correct EMBEDDED_IO_HD verilog pointer 2021-01-15 11:08:43 -08:00
Tarachand Pagarani ac355c370d merge latest changes from master 2021-01-15 00:26:25 -08:00
tpagarani 6f0dc05ffa
Merge pull request #87 from lnis-uofu/multiple_global_clocks 
add 4 global clocks
 2021-01-15 02:34:21 -05:00
Kevin Liao 806303af11 remove soft_adder, and fix Test_en from ccff 2021-01-14 20:14:04 -08:00
Kevin Liao 742d16ec39 new revised isolation io logic 2021-01-14 20:11:21 -08:00
Tarachand Pagarani 3f5409eee2 add 4 global clocks 2021-01-14 02:28:07 -08:00
Lalit Sharma ba34ebb4e5 Removing commented sections/attributes. Also corrected indentation 2021-01-13 00:48:03 -08:00
Lalit Sharma 6702de4516 Merging latest changes from master related to tile_port deprecation 2021-01-12 22:33:04 -08:00
tpagarani 40ddcdff67
Merge pull request #85 from lnis-uofu/update_tile_port 
Replacing deprecated tile_port syntax
 2021-01-13 01:22:45 -05:00
Lalit Sharma 51f11ee630 Replacing deprecated tile_port syntax 2021-01-12 21:33:53 -08:00
Kevin Liao e06fdd0a48 add annotation to support soft_adder mode 2021-01-12 21:21:53 -08:00
Kevin Liao e330b19408 Merge branch 'k4_N8_interface' of https://github.com/lnis-uofu/SOFA into k4_N8_interface 2021-01-12 21:15:15 -08:00
Kevin Liao be47862b87 created for quicklogic special io logic 2021-01-12 21:14:09 -08:00
Lalit Sharma ef4e064838 Updating openfpga with Kevin's changes done related to IO interface with an option of registered and non-registered IOs 2021-01-12 11:06:29 +05:30
Kevin Liao 489e370390 init 2021-01-11 21:11:12 -08:00
Lalit Sharma 8f1bdc2e87 Updating interface definition for QL k4_N8 device 2021-01-11 23:20:49 +05:30
tpagarani e82d2bf0d1
Merge pull request #84 from lnis-uofu/update_task_conf 
Update task conf
 2021-01-07 07:59:54 -05:00
Lalit Sharma 4128f4cd1b Enabling custom yosys script only for and gate design, will enable later for other designs when yosys submodule is updated 2021-01-07 01:15:41 -08:00
Lalit Sharma 847d0ec8f6 Adding io_reg related simple design 2021-01-06 23:24:34 -08:00
Lalit Sharma 9b3cd1f5ff Updating task template file by calling synth_quicklogic inside yosys 2021-01-06 23:19:20 -08:00
tangxifan b3f001c3fa
Merge pull request #81 from lnis-uofu/ql_ap3_arch_eval 
QL specific architecture compatible with AP3
 2021-01-06 11:08:10 -07:00
Tarachand Pagarani 1a4b1bc6b4 Disable generation of formal verification testbench due to disk space 
limitation on github actions.
Disable testcase not fitting on 32x32 device
 2021-01-05 19:44:08 -08:00
Tarachand Pagarani f04e72b5b3 create a copy of cout to connect to regular routing 2020-12-30 06:02:51 -08:00
Tarachand Pagarani 473e1d68a6 fix the carry in dangling 2020-12-29 19:04:56 -08:00