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Merge pull request #90 from lnis-uofu/ql_ccff_dummy_stdcell_pointer 

SOFA branch ql_ccff_dummy_stdcell_pointer
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tpagarani 2021-01-26 23:04:50 -05:00 committed by GitHub
parent d2240d8539 924b3d51de
commit 61655b8e1e
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2 changed files with 65 additions and 8 deletions
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29
ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -309,19 +309,32 @@ foundry middle-speed (ms) standard cell library
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<!-- new ccFF -->
<circuit_model type="ccff" name="CFGSDFFR" prefix="CFGSDFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<circuit_model type="ccff" name="QL_CCFF" prefix="QL_CCFF" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/ql_ccff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="CFG_DONE" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="CFG_DONE" lib_name="CFGE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="SI" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="CFGQN" size="1"/>
<port type="output" prefix="CFGQ" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<!-- dummy stdcell pointer -->
<circuit_model type="inv_buf" name="dummy1" prefix="dummy1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="dummy2" prefix="dummy2" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="dummy3" prefix="dummy3" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_4.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="dummy4" prefix="dummy4" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="iopad" name="IO" prefix="IO" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/ql_iso_io_logic.v">
<design_technology type="cmos"/>
@ -331,9 +344,9 @@ foundry middle-speed (ms) standard cell library
<port type="output" prefix="F2A" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1" is_config_enable="true"/>
<port type="input" prefix="CFG_DONE" lib_name="CFG_DONE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="sram" prefix="io_dir" lib_name="FPGA_IO_DIR" size="1" mode_select="true" circuit_model_name="CFGSDFFR" default_val="1"/>
<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
<port type="input" prefix="CFG_DONE" lib_name="CFG_DONE" size="1" is_global="true" default_val="0"/>
<port type="sram" prefix="io_dir" lib_name="FPGA_IO_DIR" size="1" mode_select="true" circuit_model_name="QL_CCFF" default_val="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/sky130_fd_sc_hd_wrapper.v">
<design_technology type="cmos"/>
@ -347,7 +360,7 @@ foundry middle-speed (ms) standard cell library
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="CFGSDFFR" num_regions="1"/>
<organization type="scan_chain" circuit_model_name="QL_CCFF" num_regions="1"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>

44
HDL/common/ql_ccff.v Normal file
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@ -0,0 +1,44 @@
`timescale 1ns/1ps
//-----------------------------------------------------
// Function : QuickLogic physical CCFF
// - intorduce CFGE to gate CCFF output for
// un-wanted toggling during configuration
// - intorduce test data in, SI, for DFM
//
// Note: This cell is built with Standard Cells from HD library
// It is already technology mapped and can be directly used
// for physical design
//-----------------------------------------------------
module QL_CCFF (
input RESET_B,
input SE,
input CFGE,
input D,
input SI,
output Q,
output CFGQN,
output CFGQ,
input CLK
);
sky130_fd_sc_hd__nand2_1 NAND2_CFGQN (
.A(Q),
.B(CFGE),
.X(CFGQN)
);
sky130_fd_sc_hd__inv_1 INV_CFGQN (
.A(CFGQN),
.Y(CFGQ)
);
sky130_fd_sc_hd__sdfrtp_1 SDFRTP (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SI),
.SCE(SE),
.RESET_B(RESET_B)
);
endmodule