diff --git a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
index 2029877..03ed11e 100644
--- a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -309,19 +309,32 @@ foundry middle-speed (ms) standard cell library
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@@ -331,9 +344,9 @@ foundry middle-speed (ms) standard cell library
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diff --git a/HDL/common/ql_ccff.v b/HDL/common/ql_ccff.v
new file mode 100644
index 0000000..98555d0
--- /dev/null
+++ b/HDL/common/ql_ccff.v
@@ -0,0 +1,44 @@
+`timescale 1ns/1ps
+
+//-----------------------------------------------------
+// Function : QuickLogic physical CCFF
+// - intorduce CFGE to gate CCFF output for
+// un-wanted toggling during configuration
+// - intorduce test data in, SI, for DFM
+//
+// Note: This cell is built with Standard Cells from HD library
+// It is already technology mapped and can be directly used
+// for physical design
+//-----------------------------------------------------
+module QL_CCFF (
+ input RESET_B,
+ input SE,
+ input CFGE,
+ input D,
+ input SI,
+ output Q,
+ output CFGQN,
+ output CFGQ,
+ input CLK
+);
+
+ sky130_fd_sc_hd__nand2_1 NAND2_CFGQN (
+ .A(Q),
+ .B(CFGE),
+ .X(CFGQN)
+ );
+ sky130_fd_sc_hd__inv_1 INV_CFGQN (
+ .A(CFGQN),
+ .Y(CFGQ)
+ );
+ sky130_fd_sc_hd__sdfrtp_1 SDFRTP (
+ .Q(Q),
+ .CLK(CLK),
+ .D(D),
+ .SCD(SI),
+ .SCE(SE),
+ .RESET_B(RESET_B)
+ );
+
+endmodule
+