From 84c217bc568c4c29ddb47c76fd9fb55081066b7b Mon Sep 17 00:00:00 2001 From: Kevin Liao Date: Tue, 26 Jan 2021 09:41:23 -0800 Subject: [PATCH 1/5] replace CFGSDFFR with QL_CCFF and fix testbench related --- ...avel_io_skywater130nm_fdhd_cc_openfpga.xml | 29 ++++++++++++++----- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 2029877..98fe7fd 100644 --- a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -309,19 +309,32 @@ foundry middle-speed (ms) standard cell library - + - + - + - + + + + + + + + + + + + + + @@ -331,9 +344,9 @@ foundry middle-speed (ms) standard cell library - - - + + + @@ -347,7 +360,7 @@ foundry middle-speed (ms) standard cell library - + From f0050b851d3a88eceb84e159ca6d3ee73adfd51c Mon Sep 17 00:00:00 2001 From: Kevin Liao Date: Tue, 26 Jan 2021 09:43:53 -0800 Subject: [PATCH 2/5] QuickLogic physical ccff --- HDL/common/ql_ccff.v | 55 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 HDL/common/ql_ccff.v diff --git a/HDL/common/ql_ccff.v b/HDL/common/ql_ccff.v new file mode 100644 index 0000000..aabf908 --- /dev/null +++ b/HDL/common/ql_ccff.v @@ -0,0 +1,55 @@ +`timescale 1ns/1ps + +//----------------------------------------------------- +// Function : An embedded I/O with +// - An I/O isolation signal to set +// the I/O in input mode. This is to avoid +// any unexpected output signals to damage +// circuits outside the FPGA due to configurable +// memories are not properly initialized +// This feature may not be needed if the configurable +// memory cell has a built-in set/reset functionality +// - Internal protection circuitry to ensure +// clean signals at all the SOC I/O ports +// This is to avoid +// - output any random signal +// when the I/O is in input mode, also avoid +// - driven by any random signal +// when the I/O is output mode +// +// Note: This cell is built with Standard Cells from HD library +// It is already technology mapped and can be directly used +// for physical design +//----------------------------------------------------- +module QL_CCFF ( + input RESET_B, + input SE, + input CFGE, + input D, + input SI, + output Q, + output CFGQN, + output CFGQ, + input CLK +); + + sky130_fd_sc_hd__nand2_1 NAND2_CFGQN ( + .A(Q), + .B(CFGE), + .X(CFGQN) + ); + sky130_fd_sc_hd__inv_1 INV_CFGQN ( + .A(CFGQN), + .Y(CFGQ) + ); + sky130_fd_sc_hd__sdfrtp SDFRTP ( + .Q(Q), + .CLK(CLK), + .D(D), + .SCD(SI), + .SCE(SE), + .RESET_B(RESET_B) + ); + +endmodule + From f7feca66862ae383f3eb6855005e4dee320732d8 Mon Sep 17 00:00:00 2001 From: Kevin Liao Date: Tue, 26 Jan 2021 10:10:35 -0800 Subject: [PATCH 3/5] update header for description --- HDL/common/ql_ccff.v | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/HDL/common/ql_ccff.v b/HDL/common/ql_ccff.v index aabf908..9a0026b 100644 --- a/HDL/common/ql_ccff.v +++ b/HDL/common/ql_ccff.v @@ -1,21 +1,10 @@ `timescale 1ns/1ps //----------------------------------------------------- -// Function : An embedded I/O with -// - An I/O isolation signal to set -// the I/O in input mode. This is to avoid -// any unexpected output signals to damage -// circuits outside the FPGA due to configurable -// memories are not properly initialized -// This feature may not be needed if the configurable -// memory cell has a built-in set/reset functionality -// - Internal protection circuitry to ensure -// clean signals at all the SOC I/O ports -// This is to avoid -// - output any random signal -// when the I/O is in input mode, also avoid -// - driven by any random signal -// when the I/O is output mode +// Function : QuickLogic physical CCFF +// - intorduce CFGE to gate CCFF output for +// un-wanted toggling during configuration +// - intorduce test data in, SI, for DFM // // Note: This cell is built with Standard Cells from HD library // It is already technology mapped and can be directly used From 965fbdbfead55a333f832579a44ed492211d8905 Mon Sep 17 00:00:00 2001 From: Kevin Liao Date: Tue, 26 Jan 2021 15:36:33 -0800 Subject: [PATCH 4/5] correct to sky130_fd_sc_hd__sdfrtp_1 --- HDL/common/ql_ccff.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/HDL/common/ql_ccff.v b/HDL/common/ql_ccff.v index 9a0026b..98555d0 100644 --- a/HDL/common/ql_ccff.v +++ b/HDL/common/ql_ccff.v @@ -31,7 +31,7 @@ module QL_CCFF ( .A(CFGQN), .Y(CFGQ) ); - sky130_fd_sc_hd__sdfrtp SDFRTP ( + sky130_fd_sc_hd__sdfrtp_1 SDFRTP ( .Q(Q), .CLK(CLK), .D(D), From 924b3d51de659d0d01844b23d8493b8a03011c57 Mon Sep 17 00:00:00 2001 From: Kevin Liao Date: Tue, 26 Jan 2021 15:45:59 -0800 Subject: [PATCH 5/5] correct dummy stdcell verilog pointer --- ...an_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 98fe7fd..03ed11e 100644 --- a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -324,16 +324,16 @@ foundry middle-speed (ms) standard cell library - + - + - + - +