Aram Kostanyan 2eef21a1af Fixed port names for mult_36x36		2021-10-26 19:14:43 +05:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks	2021-07-02 17:28:17 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Update fpgaflow_default_tool_path.conf	2021-09-17 14:02:26 +08:00
openfpga_arch	Fixed port names for mult_36x36	2021-10-26 19:14:43 +05:00
openfpga_cell_library	[HDL] Added a multi-mode FF design with configurable asynchronous reset	2021-07-02 11:13:03 -06:00
openfpga_shell_scripts	[Test] Bug fix	2021-06-29 18:51:28 -06:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
regression_test_scripts	Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench	2021-07-01 15:29:39 -06:00
scripts	Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py	2021-10-18 10:45:35 +00:00
tasks	[Test] Patch test case due to the changes in counter benchmarks	2021-07-02 17:57:39 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Patch architecture due to missing mode bit definition	2021-07-02 11:41:29 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00