slt b867db815f Update fpgaflow_default_tool_path.conf ... Update regex for VPR		2021-09-17 14:02:26 +08:00
..
formality_template.tcl	Updated formality python script	2019-09-27 14:00:57 -06:00
fpgaflow_default_tool_path.conf	Update fpgaflow_default_tool_path.conf	2021-09-17 14:02:26 +08:00
modelsim_proc.tcl	Added task support for modelsim script	2019-11-15 23:23:15 -07:00
modelsim_runsim.tcl	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
qlf_yosys.ys	[Script] Update quicklogic's script to output correct verilog file name	2021-03-08 21:39:44 -07:00
ys_tmpl_rewrite_flow.ys	[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'	2021-03-10 13:56:35 -07:00
ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys	[Script] Add yosys script supporting customize DFF/BRAM/DSP mapping	2021-04-21 19:50:07 -06:00
ys_tmpl_yosys_vpr_bram_dsp_flow.ys	[Script] Solved the problem on BRAM mapping in the yosys script supporting both DSP and BRAMs	2021-03-22 10:39:47 -06:00
ys_tmpl_yosys_vpr_bram_flow.ys	[Script] Update yosys script using BRAMs	2021-04-27 21:44:27 -06:00
ys_tmpl_yosys_vpr_dff_flow.ys	[Script] Patch yosys script with dff tech map	2021-04-16 20:47:18 -06:00
ys_tmpl_yosys_vpr_dsp_flow.ys	[Script] Add a template yosys script support only DSP mapping	2021-03-23 15:32:10 -06:00
ys_tmpl_yosys_vpr_flow.ys	Added fpga_flow script - Working Yosys	2019-08-09 16:49:05 -06:00
ys_tmpl_yosys_vpr_flow_with_rewrite.ys	[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'	2021-03-10 13:56:35 -07:00