ANDREW HARRIS POND 8513b8a4ff Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench		2021-07-01 15:29:39 -06:00
..
basic_reg_test.sh	[Test] Add the test cases to regression test	2021-06-29 16:08:22 -06:00
fpga_bitstream_reg_test.sh	[Test] Deploy new tests to regression test	2021-05-07 12:06:46 -06:00
fpga_sdc_reg_test.sh	[Test] Update regression test with new SDC tests	2021-04-11 20:24:32 -06:00
fpga_spice_reg_test.sh	[Test] Move regression test scripts from workflow to openfpga_flow	2021-02-16 11:55:47 -07:00
fpga_verilog_reg_test.sh	[Test] Added the new test cases to regression tests	2021-06-27 19:58:15 -06:00
iwls_benchmark_reg_test.sh	[Test] Add golden results for IWLS2005 as a simple QoR check	2021-04-22 19:27:31 -06:00
micro_benchmark_reg_test.sh	ready to merge	2021-07-01 15:28:59 -06:00
quicklogic_reg_test.sh	[Test] Deploy new test to CI	2021-02-23 19:55:07 -07:00
vtr_benchmark_reg_test.sh	[Test] Update tolerance when checking VTR benchmark QoR	2021-03-23 12:27:20 -06:00