tangxifan c05f12ac11 [core] sync up logical-to-physical configurable child mapping after physical memory build-up		2023-08-02 12:24:16 -07:00
..
annotation	[core] fixed bugs on supporting heterogeneous blocks in tile modules	2023-07-27 20:29:18 -07:00
base	[core] developing group config block support for routing module	2023-08-01 22:57:22 -07:00
fabric	[core] sync up logical-to-physical configurable child mapping after physical memory build-up	2023-08-02 12:24:16 -07:00
fpga_bitstream	[core] fixed a bug where pb/cb/sb instance name is not assigned correctly in bitstream manager under tile modules	2023-07-27 13:33:23 -07:00
fpga_sdc	[core] disable pnr sdc for tile-based fabric	2023-07-25 15:38:41 -07:00
fpga_spice	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
fpga_verilog	[core] now fpga verilog supports tile modules	2023-07-18 22:35:22 -07:00
mux_lib	Merge branch 'master' into xt_clk_arch	2023-04-19 22:17:33 +08:00
repack	[engine] code format	2023-01-20 21:52:32 -08:00
tile_direct	[core] code format	2023-06-07 18:55:34 -07:00
utils	[core] sync up logical-to-physical configurable child mapping after physical memory build-up	2023-08-02 12:24:16 -07:00
vpr_wrapper	[core] code format	2023-04-19 11:10:42 +08:00
ctag_src.sh	[engine] remove warnings	2022-08-18 15:56:18 -07:00
main.cpp	[engine] fixed syntax errors	2022-11-23 17:06:27 -08:00
openfpga_shell.i	[script] rename shared library name for tcl, so that it is straightforward to load in tcl	2022-12-01 15:59:52 -08:00