tangxifan 6607bb7e48 [core] now fpga verilog supports tile modules		2023-07-18 22:35:22 -07:00
..
fabric_verilog_options.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
fabric_verilog_options.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_api.cpp	[core] now fpga verilog supports tile modules	2023-07-18 22:35:22 -07:00
verilog_api.h	[core] now fpga verilog supports tile modules	2023-07-18 22:35:22 -07:00
verilog_auxiliary_netlists.cpp	[core] now fpga verilog supports tile modules	2023-07-18 22:35:22 -07:00
verilog_auxiliary_netlists.h	[core] now fabric netlist include mock wrapper	2023-05-26 18:49:57 -07:00
verilog_constants.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_decoders.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_decoders.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_essential_gates.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_essential_gates.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_formal_random_top_testbench.cpp	[core] fixed several bugs which causes bgf and pcf support in mock wrapper failed	2023-05-27 12:13:16 -07:00
verilog_formal_random_top_testbench.h	[engine] add missing header files after coding formatter sorts the include files	2022-10-06 18:08:57 -07:00
verilog_grid.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_grid.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_lut.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_lut.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_memory.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_memory.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_mock_fpga_wrapper.cpp	[core] now mock fpga top supports fpga core wrapper	2023-06-26 15:06:11 -07:00
verilog_mock_fpga_wrapper.h	[core] now mock fpga top supports fpga core wrapper	2023-06-26 15:06:11 -07:00
verilog_module_writer.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_module_writer.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_mux.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_mux.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_port_types.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_preconfig_top_module.cpp	[core] code format	2023-06-26 10:06:17 -07:00
verilog_preconfig_top_module.h	[core] supporting io naming for verilog testbench generators	2023-06-25 15:29:27 -07:00
verilog_routing.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_routing.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_shift_register_banks.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_shift_register_banks.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_simulation_info_writer.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_simulation_info_writer.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_submodule.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_submodule.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_submodule_utils.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_submodule_utils.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_testbench_options.cpp	[core] supporting io naming for verilog testbench generators	2023-06-25 15:29:27 -07:00
verilog_testbench_options.h	[core] supporting io naming for verilog testbench generators	2023-06-25 15:29:27 -07:00
verilog_testbench_utils.cpp	[core] fixed the bug when using fpga_core instead of fpga_top	2023-06-25 18:03:15 -07:00
verilog_testbench_utils.h	[core] supporting io naming for verilog testbench generators	2023-06-25 15:29:27 -07:00
verilog_tile.cpp	[core] now fpga verilog supports tile modules	2023-07-18 22:35:22 -07:00
verilog_tile.h	[core] now fpga verilog supports tile modules	2023-07-18 22:35:22 -07:00
verilog_top_module.cpp	[core] format	2023-06-18 21:18:35 -07:00
verilog_top_module.h	[core] format	2023-06-18 21:18:35 -07:00
verilog_top_testbench.cpp	[core] supporting io naming for verilog testbench generators	2023-06-25 15:29:27 -07:00
verilog_top_testbench.h	[core] supporting io naming for verilog testbench generators	2023-06-25 15:29:27 -07:00
verilog_top_testbench_constants.h	[core] developing testbench generator for ccff v2	2023-04-24 11:36:21 +08:00
verilog_top_testbench_memory_bank.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_top_testbench_memory_bank.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_wire.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_wire.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_writer_utils.cpp	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00
verilog_writer_utils.h	[engine] update source files subject to code formatting rules	2022-10-06 17:08:50 -07:00