OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/base
tangxifan f779ad7ecf bug fixing for global and gpio port wiring; start refactoring top-level module 2019-10-14 15:53:04 -06:00
..
bitstream_context.h Start developing BitstreamContext 2019-09-13 21:27:47 -06:00
bitstream_context_fwd.h Start developing BitstreamContext 2019-09-13 21:27:47 -06:00
device_coordinator.cpp Add copy constructor for RRChan, RRSwitchBlock etc. 2019-05-27 15:44:34 -06:00
device_coordinator.h Add copy constructor for RRChan, RRSwitchBlock etc. 2019-05-27 15:44:34 -06:00
fpga_x2p_api.c rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
fpga_x2p_api.h rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
fpga_x2p_backannotate_utils.c fixed critical bugs in pass_tracks identification and update regression test for tileable arch 2019-06-25 21:59:38 -06:00
fpga_x2p_backannotate_utils.h rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
fpga_x2p_bitstream_utils.c Rename SCFF to CCFF, configuration chain flip flop 2019-09-26 11:32:57 -06:00
fpga_x2p_bitstream_utils.h Finish renaming SCFF to CCFF 2019-09-26 14:04:40 -06:00
fpga_x2p_globals.c rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
fpga_x2p_globals.h rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
fpga_x2p_lut_utils.c cleaned unused variables 2019-05-13 14:45:02 -06:00
fpga_x2p_lut_utils.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
fpga_x2p_mem_utils.cpp Refactoring Verilog generation intermediate level of pb_types and SRAM port generation 2019-10-11 21:43:47 -06:00
fpga_x2p_mem_utils.h Refactoring Verilog generation intermediate level of pb_types and SRAM port generation 2019-10-11 21:43:47 -06:00
fpga_x2p_mux_utils.c refactoring mux Verilog generation for switch blocks 2019-09-26 20:59:19 -06:00
fpga_x2p_mux_utils.h updated bitstream generator for local encoders 2019-08-06 14:17:56 -06:00
fpga_x2p_naming.cpp bug fixing for global and gpio port wiring; start refactoring top-level module 2019-10-14 15:53:04 -06:00
fpga_x2p_naming.h bug fixing for global and gpio port wiring; start refactoring top-level module 2019-10-14 15:53:04 -06:00
fpga_x2p_pbtypes_utils.c start plug in new Verilog writer. Start debugging 2019-10-10 22:02:46 -06:00
fpga_x2p_pbtypes_utils.h start plug in new Verilog writer. Start debugging 2019-10-10 22:02:46 -06:00
fpga_x2p_rr_graph_utils.c many bug fixing and now start improving the routability of tileable rr_graph 2019-06-24 17:33:29 -06:00
fpga_x2p_rr_graph_utils.h many bug fixing and now start improving the routability of tileable rr_graph 2019-06-24 17:33:29 -06:00
fpga_x2p_setup.c Rename SCFF to CCFF, configuration chain flip flop 2019-09-26 11:32:57 -06:00
fpga_x2p_setup.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
fpga_x2p_timing_utils.c developed new rotating methods for RRSwitchBlocks, debugging ongoing 2019-05-26 23:35:30 -06:00
fpga_x2p_timing_utils.h Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
fpga_x2p_types.h keep developing tileable rr_graph, track2ipin and opin2track to go 2019-06-19 21:30:16 -06:00
fpga_x2p_unique_routing.c speeding up identifying unique modules in routing 2019-07-14 13:49:20 -06:00
fpga_x2p_unique_routing.h rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
fpga_x2p_utils.c start adding memory circuit to Switch blocks 2019-09-27 18:08:37 -06:00
fpga_x2p_utils.h Rename SCFF to CCFF, configuration chain flip flop 2019-09-26 11:32:57 -06:00
link_arch_circuit_lib.cpp refactored port addition for pb_types in Verilog generation 2019-10-08 14:03:17 -06:00
link_arch_circuit_lib.h rework on the circuit model ports and start prototyping mux Verilog generation 2019-08-20 15:24:53 -06:00
module_manager.cpp add gpio ports to pb_type modules 2019-10-13 16:23:22 -06:00
module_manager.h add gpio ports to pb_type modules 2019-10-13 16:23:22 -06:00
module_manager_fwd.h developing verilog writer for generic module graph 2019-10-10 20:09:55 -06:00
module_manager_utils.cpp bug fixing for global and gpio port wiring; start refactoring top-level module 2019-10-14 15:53:04 -06:00
module_manager_utils.h add memory ports and nets to intermediate pb_types 2019-10-13 17:45:32 -06:00
quicksort.c upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
quicksort.h upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
rr_blocks.cpp Buggy version but need help on debugging 2019-10-01 14:49:42 -06:00
rr_blocks.h Bug fix 2019-09-16 10:57:52 -06:00
rr_blocks_naming.cpp c++ string is not working, use char which is stable 2019-06-13 18:38:46 -06:00
rr_blocks_naming.h add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB 2019-06-06 23:45:21 -06:00
rr_blocks_utils.cpp refactored shared config bits calculation 2019-10-06 16:57:53 -06:00
rr_blocks_utils.h refactored shared config bits calculation 2019-10-06 16:57:53 -06:00
write_rr_blocks.cpp fixed the bug in determine passing wires for rr_gsb 2019-06-26 10:50:23 -06:00
write_rr_blocks.h update rr_block writer to include IPINs in XML files 2019-06-25 11:17:22 -06:00