tangxifan bd6a0c6a55 refactored grid instance addition to top module		2019-10-14 17:47:10 -06:00
..
base	bug fixing for global and gpio port wiring; start refactoring top-level module	2019-10-14 15:53:04 -06:00
bitstream	replace spice_models with circuit model in bitstream generator	2019-08-16 16:36:49 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb	2019-05-13 14:45:57 -06:00
spice	Rename SCFF to CCFF, configuration chain flip flop	2019-09-26 11:32:57 -06:00
verilog	refactored grid instance addition to top module	2019-10-14 17:47:10 -06:00