| .. |
|
FIR_filter
|
[Benchmark] Add micro benchmark for FIR filter
|
2021-02-18 19:37:44 -07:00 |
|
FSM_three_code
|
enrich micro benchmarks
|
2020-07-22 12:33:52 -06:00 |
|
RISC_posedge_clk
|
add regression test to track runtime on big fpga devices using practical benchmarks
|
2020-07-28 12:38:42 -06:00 |
|
SAPone
|
add regression test to track runtime on big fpga devices using practical benchmarks
|
2020-07-28 12:38:42 -06:00 |
|
adder
|
[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``
|
2021-06-30 15:29:13 -06:00 |
|
and2
|
Added 'basic_tests/verific_test' test-case.
|
2021-11-01 18:20:57 +05:00 |
|
and2_latch
|
Added 'basic_tests/verific_test' test-case.
|
2021-11-01 18:20:57 +05:00 |
|
and2_latch_2clock
|
[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
|
2021-04-21 14:03:51 -06:00 |
|
and2_or2
|
[Benchmark] Bug fix in the and2_or2 benchmark
|
2020-09-17 10:35:13 -06:00 |
|
and2_pipelined
|
[Benchmark] Bug fix in pipelined and2 benchmark
|
2021-01-10 10:27:59 -07:00 |
|
and4
|
[HDL] Add more micro benchmarks for counter, and-gate and mac unit
|
2021-06-21 16:48:35 -06:00 |
|
asyn_spram_4x1
|
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)
|
2021-01-29 10:19:05 -07:00 |
|
blinking
|
[Benchmark] Add microbenchmark 1-bit blinking
|
2021-05-06 15:17:27 -06:00 |
|
clk_divider
|
[benchmark] add clock divider
|
2023-01-13 16:39:06 -08:00 |
|
clk_gate
|
[test] fixed a few bugs
|
2022-09-29 15:32:31 -07:00 |
|
config_loader
|
added signal gen regression test to shell script
|
2021-06-30 16:18:09 -06:00 |
|
counters
|
[hdl] add a counter design which is triggered by negative edges
|
2022-05-09 16:41:21 +08:00 |
|
discrete_dffn
|
[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
|
2023-01-15 13:09:40 -08:00 |
|
dual_port_ram_1k
|
[Benchmark] Add 1k DPRAM benchmark which can fit new arch
|
2021-04-28 11:26:31 -06:00 |
|
dual_port_ram_16k
|
[Benchmark] Bug fix in dual port ram 16k benchmark
|
2021-04-27 23:33:20 -06:00 |
|
fifo/rtl
|
[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
|
2021-04-27 22:09:10 -06:00 |
|
mac
|
[HDL] Add more micro benchmarks for counter, and-gate and mac unit
|
2021-06-21 16:48:35 -06:00 |
|
mult
|
[test] adding a new test case to validate the bitstream overloading for DSP blocks
|
2023-01-24 14:58:52 -08:00 |
|
or2
|
Added 'basic_tests/verific_test' test-case.
|
2021-11-01 18:20:57 +05:00 |
|
pipelined_8bit_adder
|
[Benchmark] move benchmarks to microbenchmark category
|
2021-04-27 22:12:30 -06:00 |
|
routing_test
|
bug fixed in routing_test.v. Deployed to regression tests
|
2020-06-11 19:31:01 -06:00 |
|
rst_on_lut
|
[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
|
2022-09-12 10:43:21 -07:00 |
|
signal_gen
|
fixed tab spacing
|
2021-07-01 16:42:04 -06:00 |
|
syn_spram_4x1
|
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)
|
2021-01-29 10:19:05 -07:00 |
|
test_mode_low
|
Added test_mode_low benchmark
|
2020-06-11 19:31:01 -06:00 |
|
test_modes
|
[Benchmark] move benchmarks to microbenchmark category
|
2021-04-27 22:12:30 -06:00 |
|
two_dff_inv_rst
|
[benchmark] syntax
|
2023-01-18 18:34:24 -08:00 |
d60d0540da