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check_tile_annotation.cpp
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[Tool] Enhance port attribute checks in tile annotation data structure
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2020-11-11 13:41:05 -07:00 |
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check_tile_annotation.h
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[Tool] Add check codes for tile annotation
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2020-11-11 12:03:13 -07:00 |
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circuit_library_utils.cpp
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[FPGA-SPICE] Add auxiliary SPICE netlist writer
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2020-09-20 12:53:28 -06:00 |
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circuit_library_utils.h
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[FPGA-SPICE] Add auxiliary SPICE netlist writer
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2020-09-20 12:53:28 -06:00 |
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decoder_library_utils.cpp
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
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decoder_library_utils.h
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
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device_rr_gsb_utils.cpp
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add compact_routing hierarchy command
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2020-02-11 17:40:37 -07:00 |
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device_rr_gsb_utils.h
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add compact_routing hierarchy command
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2020-02-11 17:40:37 -07:00 |
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fabric_bitstream_utils.cpp
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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fabric_bitstream_utils.h
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[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
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2020-10-30 17:29:04 -06:00 |
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fabric_global_port_info_utils.cpp
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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fabric_global_port_info_utils.h
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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lut_utils.cpp
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Critical patch on repacking about wire LUT support.
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2020-04-19 16:42:31 -06:00 |
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lut_utils.h
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add truth table build up for physical LUTs
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2020-02-25 22:39:42 -07:00 |
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memory_utils.cpp
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add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
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2020-06-11 19:31:12 -06:00 |
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memory_utils.h
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |
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module_manager_utils.cpp
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[Tool] Remove redundant assertation
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2020-11-09 09:42:39 -07:00 |
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module_manager_utils.h
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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mux_utils.cpp
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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mux_utils.h
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move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
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2020-02-11 21:02:58 -07:00 |
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openfpga_atom_netlist_utils.cpp
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bug fixed for clock names
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2020-02-27 16:51:55 -07:00 |
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openfpga_atom_netlist_utils.h
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bug fixed for clock names
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2020-02-27 16:51:55 -07:00 |
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openfpga_device_grid_utils.cpp
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[Tool] Change the i/o numbering to the clockwise sequence
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2020-11-13 15:00:25 -07:00 |
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openfpga_device_grid_utils.h
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[Tool] Refactor the codes for walking through io blocks
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2020-11-03 13:21:50 -07:00 |
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openfpga_physical_tile_utils.cpp
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[Tool] Extend the support on global tile port for I/O tiles
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2020-11-11 15:09:40 -07:00 |
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openfpga_physical_tile_utils.h
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[Tool] Extend the support on global tile port for I/O tiles
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2020-11-11 15:09:40 -07:00 |
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pb_graph_utils.cpp
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add mux library builder
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2020-02-12 14:58:23 -07:00 |
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pb_graph_utils.h
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add mux library builder
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2020-02-12 14:58:23 -07:00 |
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pb_type_utils.cpp
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[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
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2020-09-02 22:16:10 -06:00 |
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pb_type_utils.h
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[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
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2020-09-02 22:16:10 -06:00 |
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physical_pb_utils.cpp
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bug fixed in identifying wired LUT
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2020-04-22 17:28:16 -06:00 |
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physical_pb_utils.h
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Critical patch on repacking about wire LUT support.
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2020-04-19 16:42:31 -06:00 |
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rr_gsb_utils.cpp
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update bitstream generator to use sorted edges
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2020-03-08 15:36:47 -06:00 |
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rr_gsb_utils.h
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update bitstream generator to use sorted edges
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2020-03-08 15:36:47 -06:00 |
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simulation_utils.cpp
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[Tool] Rework simulation time period to be sync with actual stimuli
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2020-12-02 22:58:13 -07:00 |
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simulation_utils.h
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[Tool] Rework simulation time period to be sync with actual stimuli
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2020-12-02 22:58:13 -07:00 |
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