tangxifan
|
4aa6264b1c
|
[Tool] Rework simulation time period to be sync with actual stimuli
|
2020-12-02 22:58:13 -07:00 |
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tangxifan
|
3f91b8433e
|
[Tool] Change the i/o numbering to the clockwise sequence
|
2020-11-13 15:00:25 -07:00 |
|
tangxifan
|
372fb261fd
|
[Tool] Extend the support on global tile port for I/O tiles
|
2020-11-11 15:09:40 -07:00 |
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tangxifan
|
e627b6dd5d
|
[Tool] Enhance port attribute checks in tile annotation data structure
|
2020-11-11 13:41:05 -07:00 |
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tangxifan
|
9cbc374b33
|
[Tool] Add check codes for tile annotation
|
2020-11-11 12:03:13 -07:00 |
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tangxifan
|
c61ec5a8b8
|
[Tool] Bug fix for defining global ports from tiles
|
2020-11-10 20:31:14 -07:00 |
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tangxifan
|
dcb50e4f19
|
[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
|
tangxifan
|
5fe9c27600
|
[Tool] Remove redundant assertation
|
2020-11-09 09:42:39 -07:00 |
|
tangxifan
|
ba0120bd76
|
[Tool] Remove the limitation on requiring Qb ports for CCFF
|
2020-11-06 11:10:04 -07:00 |
|
tangxifan
|
9b0617ffe6
|
[Tool] Bug fix for mappable I/O support
|
2020-11-04 20:45:51 -07:00 |
|
tangxifan
|
37c10f0cb5
|
[Tool] Add mappable I/O support and enhance I/O support
|
2020-11-04 20:21:49 -07:00 |
|
tangxifan
|
4a2874b2bc
|
[Tool] Refactor the codes for walking through io blocks
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2020-11-03 13:21:50 -07:00 |
|
tangxifan
|
b78f8bec16
|
[Tool] Bug fixed for multi-region configuration frame
|
2020-10-30 21:19:20 -06:00 |
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tangxifan
|
5bcd559851
|
[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
|
2020-10-30 17:29:04 -06:00 |
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tangxifan
|
987eccf586
|
[Tool] Bug fix in multi-region memory bank; Basic test passed
|
2020-10-29 16:26:45 -06:00 |
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tangxifan
|
448e88645a
|
[Tool] Support multiple memory banks in top-level module
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2020-10-29 12:42:03 -06:00 |
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tangxifan
|
e988e35f81
|
[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
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2020-09-29 12:22:10 -06:00 |
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tangxifan
|
222bc86cbf
|
[FPGA-SPICE] Add auxiliary SPICE netlist writer
|
2020-09-20 12:53:28 -06:00 |
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tangxifan
|
04070fd4ca
|
[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
|
2020-09-02 22:16:10 -06:00 |
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tangxifan
|
a4a38f8156
|
support multi-bit power gate ports in FPGA-SPICE
|
2020-07-22 20:04:39 -06:00 |
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tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |
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tangxifan
|
824b56f14c
|
fabric key can now accept instance name only; decoders are no longer part of the key
|
2020-07-06 16:42:33 -06:00 |
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tangxifan
|
83e26adf90
|
add module usage types for future FPGA-SPICE development
|
2020-07-04 22:33:54 -06:00 |
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tangxifan
|
033c92c365
|
precisely reserve memory for child blocks in bitstream manager
|
2020-07-03 22:47:21 -06:00 |
|
tangxifan
|
57e6c84252
|
add reserve net sources and sinks to module manager
|
2020-06-29 22:49:11 -06:00 |
|
tangxifan
|
66746f69da
|
optimizing memory efficiency by reserving nets in module manager
|
2020-06-29 21:27:43 -06:00 |
|
tangxifan
|
5368485bd6
|
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
0bee70bee6
|
finish memory bank configuration protocol support.
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
0e16ee1030
|
add configuration bus nets for memory bank decoders at top module
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
fa8dfc1fbd
|
add configuration protocol ports to top module for memory bank organization
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
fbe05963e0
|
add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8298bbff78
|
bug fixed in the fabric bitstream for frame-based configurable memories.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
bf9f62f0f7
|
keep bug fixing for frame-based configuration protocol.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
c696e3d20f
|
refine frame-based memory addition to compact the area
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
290dd1a8a6
|
add frame decoder builder to all the module graph builder except the top-level
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
8864920460
|
add frame-based memory module builder
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
3a26bb5eef
|
add advanced check in configurable memories
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
e089b0ef22
|
use constant string for inverted port naming
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
bf841b9a8e
|
bug fixed in identifying wired LUT
|
2020-04-22 17:28:16 -06:00 |
|
tangxifan
|
e10cafe0a5
|
Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
|
2020-04-19 16:42:31 -06:00 |
|
tangxifan
|
e6c896d583
|
now inout must be global port and I/O port so that it will appear in the top-level module
|
2020-04-08 16:54:08 -06:00 |
|
tangxifan
|
bcb86801fa
|
bug fixed in gpio naming for module manager ports
|
2020-04-05 17:26:44 -06:00 |
|
tangxifan
|
5f4e7dc5d4
|
support gpinput and gpoutput ports in module manager and circuit library
|
2020-04-05 16:52:21 -06:00 |
|
tangxifan
|
8b583b7917
|
debugging spy port builder in module manager
|
2020-04-05 16:01:25 -06:00 |
|
tangxifan
|
836f722f20
|
start supporting global output ports in module manager
|
2020-04-05 15:19:46 -06:00 |
|
tangxifan
|
7c9c2451f2
|
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
|
2020-03-27 16:03:42 -06:00 |
|
tangxifan
|
b6bdf78d95
|
bug fixed for heterogeneous block instances in top module
|
2020-03-24 17:39:26 -06:00 |
|
tangxifan
|
fc6abc13fd
|
add physical tile utils to identify pins that have Fc=0
|
2020-03-21 21:02:47 -06:00 |
|
tangxifan
|
b80e26e711
|
update bitstream generator to use sorted edges
|
2020-03-08 15:36:47 -06:00 |