tangxifan d11a3d9fef [Tool] Avoid outputting signal initialization codes because they are bulky		2020-12-06 14:29:16 -07:00
..
annotation	[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches	2020-12-02 19:36:36 -07:00
base	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fabric	[Tool] Remove register ports for mini local encoders (1-bit data out)	2020-12-06 14:21:54 -07:00
fpga_bitstream	[Tool] Adapted tools to support I/O in center grid	2020-12-04 18:50:13 -07:00
fpga_sdc	[Tool] Adapted tools to support I/O in center grid	2020-12-04 18:50:13 -07:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[Tool] Avoid outputting signal initialization codes because they are bulky	2020-12-06 14:29:16 -07:00
mux_lib	bug fix in lut and mux module generation on supporting spypads	2020-04-22 14:41:16 -06:00
repack	[Tool] Relex logic block checking codes to skip zero-capacity nodes	2020-11-02 16:57:19 -07:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Tool] Rework simulation time period to be sync with actual stimuli	2020-12-02 22:58:13 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	start transplanting FPGA-SPICE	2020-07-05 12:10:12 -06:00