OpenFPGA/openfpga_flow/VerilogNetlists
tangxifan 7591060fbd [Architecture] Add configurable latch Verilog designs and assoicated architectures 2020-09-23 21:45:06 -06:00
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adder.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
aib.v try to add aib test case. bug found 2020-04-12 14:54:45 -06:00
config_latch.v [Architecture] Bug fix in configurable latch Verilog HDL 2020-09-23 18:28:45 -06:00
config_latch_neg_rst.v [Architecture] Patch configurable latch Verilog HDL with resetb 2020-09-23 18:30:48 -06:00
config_latch_set.v [Architecture] Add configurable latch Verilog designs and assoicated architectures 2020-09-23 21:45:06 -06:00
config_latch_set_reset.v [Architecture] Add configurable latch Verilog designs and assoicated architectures 2020-09-23 21:45:06 -06:00
dpram.v Adding heterogeneous synthesis requirements 2019-12-03 16:09:26 -07:00
dpram1k.v [Architecture] Add verilog HDL for dual-port BRAM 1k 2020-09-22 12:23:28 -06:00
dpram16k.v add test case of BRAM to Travis CI 2020-04-12 14:27:05 -06:00
dpram_tb.v Adding DPRAM behavioural Verilog netlist and its TB 2019-12-03 13:58:20 -07:00
ff.v add register chain and scan chain to Travis CI 2020-04-12 15:28:22 -06:00
ff_en.v [Architecture] Bug fix in configurable latch Verilog HDL 2020-09-23 18:28:45 -06:00
ff_tb.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
frac_mem_32k.v add Verilog design for fracturable 32k memory 2020-08-18 21:13:46 -06:00
io.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
lb_tb.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
lut6.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
mult_32x32.v [Architecture] Add Verilog HDL for fracturable 32-bit multiplier 2020-09-22 15:15:19 -06:00
mult_36x36.v add 36-bit fracturable multiplier Verilog 2020-08-18 14:06:08 -06:00
mux2.v bug fixed for std cell MUX2 architecture and add the case to regression tests 2019-11-06 16:06:47 -07:00
mux_tb.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
sram.v update arch to support reset signal for SRAm 2020-06-11 19:31:14 -06:00
sram_tb.v Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00