38 lines
877 B
Verilog
38 lines
877 B
Verilog
//-----------------------------------------------------
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// Design Name : config_latch
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// File Name : config_latch.v
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// Function : A Configurable Latch where data storage
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// can be updated when wl is enabled
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// Set is active high
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// Coder : Xifan TANG
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//-----------------------------------------------------
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module config_latch_set (
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input set, // Reset input
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input wl, // Data Enable
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input bl, // Data Input
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output Q, // Q output
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output Qb // Q output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ (set or bl or wl) begin
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if (set) begin
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q_reg <= 1'b1;
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end else if (1'b1 == wl) begin
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q_reg <= bl;
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end
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end
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`ifndef ENABLE_FORMAL_VERIFICATION
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// Wire q_reg to Q
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assign Q = q_reg;
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assign Qb = ~q_reg;
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`else
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assign Q = 1'bZ;
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assign Qb = !Q;
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`endif
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endmodule
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