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FIR_filter
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[Benchmark] Add micro benchmark for FIR filter
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2021-02-18 19:37:44 -07:00 |
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FSM_three_code
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enrich micro benchmarks
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2020-07-22 12:33:52 -06:00 |
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RISC_posedge_clk
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add regression test to track runtime on big fpga devices using practical benchmarks
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2020-07-28 12:38:42 -06:00 |
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SAPone
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add regression test to track runtime on big fpga devices using practical benchmarks
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2020-07-28 12:38:42 -06:00 |
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adder_8
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[Benchmark] Change to use adder lut4 to be consistent with architecture
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2021-02-03 09:37:48 -07:00 |
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and2
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[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
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2021-02-09 15:41:21 -07:00 |
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and2_latch
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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and2_latch_2clock
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[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
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2021-04-21 14:03:51 -06:00 |
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and2_or2
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[Benchmark] Bug fix in the and2_or2 benchmark
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2020-09-17 10:35:13 -06:00 |
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and2_pipelined
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[Benchmark] Bug fix in pipelined and2 benchmark
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2021-01-10 10:27:59 -07:00 |
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and4
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[HDL] Add more micro benchmarks for counter, and-gate and mac unit
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2021-06-21 16:48:35 -06:00 |
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asyn_spram_4x1
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Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)
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2021-01-29 10:19:05 -07:00 |
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blinking
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[Benchmark] Add microbenchmark 1-bit blinking
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2021-05-06 15:17:27 -06:00 |
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counter
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bug fix in the regression test due to benchmark changes
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2020-07-22 13:17:05 -06:00 |
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counter4bit_2clock
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[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
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2021-01-13 15:43:31 -07:00 |
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counter_128bit_async_reset
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[HDL] Add more micro benchmarks for counter, and-gate and mac unit
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2021-06-21 16:48:35 -06:00 |
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counter_128bit_async_resetb
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[HDL] Bug fix in Verilog syntax
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2021-06-22 16:18:46 -06:00 |
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counter_async_reset
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[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
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2021-04-16 20:14:48 -06:00 |
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dual_port_ram_1k
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[Benchmark] Add 1k DPRAM benchmark which can fit new arch
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2021-04-28 11:26:31 -06:00 |
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dual_port_ram_16k
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[Benchmark] Bug fix in dual port ram 16k benchmark
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2021-04-27 23:33:20 -06:00 |
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fifo/rtl
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[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
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2021-04-27 22:09:10 -06:00 |
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mac
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[HDL] Add more micro benchmarks for counter, and-gate and mac unit
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2021-06-21 16:48:35 -06:00 |
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or2
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bug fix in read architecture bitstream and regression tests
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2020-07-27 19:37:05 -06:00 |
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pipelined_8bit_adder
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[Benchmark] move benchmarks to microbenchmark category
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2021-04-27 22:12:30 -06:00 |
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routing_test
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bug fixed in routing_test.v. Deployed to regression tests
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2020-06-11 19:31:01 -06:00 |
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syn_spram_4x1
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Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)
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2021-01-29 10:19:05 -07:00 |
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test_mode_low
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Added test_mode_low benchmark
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2020-06-11 19:31:01 -06:00 |
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test_modes
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[Benchmark] move benchmarks to microbenchmark category
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2021-04-27 22:12:30 -06:00 |
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