Go to file
komaljaved-rs 6d11dc275d
Update ci_test.yml
2021-07-01 16:01:38 +05:00
.github Update ci_test.yml 2021-07-01 16:01:38 +05:00
RTL_Benchmark@16bc04733b updated submodule 2021-07-01 15:14:59 +05:00
abc Add latest abc and update ace dependence 2019-05-03 18:56:03 -06:00
ace2 Now we use the ace from VTR 2019-07-16 17:00:09 -06:00
cmake copy missing cmake modules from vtr project 2020-01-03 21:57:19 -05:00
docker Bug fix on Docker build and upload on master (#202) 2021-01-29 11:16:57 -07:00
docs [Doc] Remove ``define_simulation.v`` since it is no longer needed. 2021-06-29 15:38:35 -06:00
libopenfpga [Tool] Add postfix removal support in write_io_mapping command 2021-06-18 16:13:50 -06:00
libs [Tool] Patch to remove compiler warnings 2021-02-04 16:54:04 -07:00
openfpga [Tool] Bug fix for redundant endif in netlists 2021-06-29 17:02:16 -06:00
openfpga_flow added ci_scripts 2021-07-01 15:07:37 +05:00
vpr [Tool] Add illustrative comments to tileable rr_graph generator 2021-04-26 11:57:17 -06:00
yosys@f44a4f9086 update yosys module with async preset support 2021-03-10 10:14:42 -08:00
.dockerignore Bug fix on Docker build and upload on master (#202) 2021-01-29 11:16:57 -07:00
.gitignore Github action optimizations 2020-12-10 14:35:19 -07:00
.gitmodules added ci_scripts 2021-07-01 15:07:37 +05:00
.readthedocs.yml Support SVG in Sphinx Latex building (#220) 2021-02-07 18:53:16 -07:00
CMakeLists.txt Update CMakeLists.txt 2021-04-26 20:51:54 -06:00
LICENSE Create LICENSE 2018-06-26 21:52:08 -07:00
Makefile Adding target compile in Makefile that just compiles without updating submodules 2020-12-14 09:25:50 -08:00
README.md Update README.md 2021-04-05 11:37:43 -06:00
ci_test.sh added ci_scripts 2021-07-01 15:07:37 +05:00
openfpga.sh [Bugfix] Added shell globstar 2021-02-08 14:07:01 -07:00
requirements.txt [Cleanup] Removed deadcode 2021-02-03 10:35:14 -07:00

README.md

Getting Started with OpenFPGA

linux build Documentation Status

Introduction

The award-winning OpenFPGA framework is the first open-source FPGA IP generator supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.

If this is the first time you learn OpenFPGA, we strongly recommend you to watch the introduction video about OpenFPGA

A quick overview of OpenFPGA tools can be found here. We also recommend potential users to checkout the summary of technical capabilities before compiling.

Compilation

A tutorial video about how-to-compile can be found here

Before start, we strongly recommend you to read the required dependencies at compilation guidelines. It also includes detailed information about docker image.


Compilation Steps:

# Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA
make all

Quick Compilation Verification

To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository.

python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs

Python3 and iVerilog v10.1+ are required. GUI will pop-up if enabled during compilation.


Supported Operating Systems

We currently target OpenFPGA for:

  1. Ubuntu 18.04
  2. Red Hat 7.5

The tool was tested with these operating systems. It might work with earlier versions and other distributions.

Documentation

OpenFPGA's full documentation includes tutorials, descriptions of the design flow, and tool options.

Tutorials

You can find a set of tutorials, with which you get familiar with the tool and use OpenFPGA in various purposes.