Aram Kostanyan 397f2e71f1 Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.		2022-01-19 20:43:26 +05:00
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basic_reg_test.sh	Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.	2022-01-19 20:43:26 +05:00
basic_reg_yosys_only_test.sh	basic reg test updated	2022-01-14 15:44:26 +05:00
fpga_bitstream_reg_test.sh	[Test] Deploy news test to fpga-bitstream regression tests	2021-10-05 19:01:03 -07:00
fpga_sdc_reg_test.sh	[Test] Update regression test with new SDC tests	2021-04-11 20:24:32 -06:00
fpga_spice_reg_test.sh	[Test] Move regression test scripts from workflow to openfpga_flow	2021-02-16 11:55:47 -07:00
fpga_verilog_reg_test.sh	[Test] Add new test case (DSP with registers) into FPGA-Verilog regression tests	2022-01-02 20:21:58 -08:00
iwls_benchmark_reg_test.sh	[Test] Add golden results for IWLS2005 as a simple QoR check	2021-04-22 19:27:31 -06:00
micro_benchmark_reg_test.sh	ready to merge	2021-07-01 15:28:59 -06:00
quicklogic_reg_test.sh	re-enable counter_5clock,sdc_controller, lut_adder tests	2021-11-19 18:06:06 +05:30
vtr_benchmark_reg_test.sh	[Test] Update tolerance when checking VTR benchmark QoR	2021-03-23 12:27:20 -06:00