| .. |
|
verilog_api.c
|
fixed bugs in configure pb_rr_graph and dependence on testbenches
|
2019-08-16 18:20:30 -06:00 |
|
verilog_api.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_autocheck_top_testbench.c
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
|
verilog_autocheck_top_testbench.h
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_compact_netlist.c
|
rework on the circuit model ports and start prototyping mux Verilog generation
|
2019-08-20 15:24:53 -06:00 |
|
verilog_compact_netlist.h
|
Snapshot of progress
|
2019-07-02 10:10:48 -06:00 |
|
verilog_decoder.c
|
fixed a bug in Verilog generator supporting SRAM5T
|
2019-06-13 14:42:39 -06:00 |
|
verilog_decoder.h
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
verilog_essential_gates.cpp
|
managed to plug in refactored essential gates, dead codes to be removed
|
2019-08-21 21:50:26 -06:00 |
|
verilog_essential_gates.h
|
renaming files
|
2019-08-20 21:01:38 -06:00 |
|
verilog_formal_random_top_testbench.c
|
Update Testbenches to increase accuracy + commented compact routing option until debug
|
2019-06-26 10:01:12 -06:00 |
|
verilog_formal_random_top_testbench.h
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_formality_autodeck.c
|
cleaned unused variables
|
2019-05-13 14:45:02 -06:00 |
|
verilog_formality_autodeck.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_global.c
|
implementing the local encoders
|
2019-08-06 14:17:55 -06:00 |
|
verilog_global.h
|
rework on the circuit model ports and start prototyping mux Verilog generation
|
2019-08-20 15:24:53 -06:00 |
|
verilog_include_netlists.c
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
verilog_include_netlists.h
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
verilog_modelsim_autodeck.c
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_modelsim_autodeck.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_mux.cpp
|
try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)
|
2019-08-21 22:45:48 -06:00 |
|
verilog_mux.h
|
renaming files
|
2019-08-20 21:01:38 -06:00 |
|
verilog_pbtypes.c
|
try to fix the bug in clock net identification
|
2019-08-13 16:47:28 -06:00 |
|
verilog_pbtypes.h
|
Latest version, not stable yet but close
|
2019-07-09 08:34:01 -06:00 |
|
verilog_primitives.c
|
Bug fix for non fracturable LUT
|
2019-08-14 09:32:15 -06:00 |
|
verilog_primitives.h
|
Include new files in the parameter spreading
|
2019-07-01 11:27:48 -06:00 |
|
verilog_report_timing.c
|
Explicit verilog final push
|
2019-07-16 13:13:30 -06:00 |
|
verilog_report_timing.h
|
updated bitstream to use new RRSwitchBlock as well as the report timing engine
|
2019-05-24 12:54:10 -06:00 |
|
verilog_routing.c
|
use single subckt for switch box again, to abolish the multi-module subckt
|
2019-08-13 16:11:04 -06:00 |
|
verilog_routing.h
|
Snapshot of progress
|
2019-07-02 10:10:48 -06:00 |
|
verilog_sdc.c
|
Explicit verilog final push
|
2019-07-16 13:13:30 -06:00 |
|
verilog_sdc.h
|
Division between horizontal and vertical analysis
|
2019-06-25 13:44:41 -06:00 |
|
verilog_sdc_pb_types.c
|
Break memories even in the clb sdc
|
2019-06-16 14:27:29 -06:00 |
|
verilog_sdc_pb_types.h
|
clean up warnings in SDC pb_type generator
|
2019-05-24 15:23:38 -06:00 |
|
verilog_submodule_utils.cpp
|
minor tuning on the delay assignment
|
2019-08-21 23:11:54 -06:00 |
|
verilog_submodule_utils.h
|
complete refacotriing the inv and buf part in submodules
|
2019-08-21 14:54:05 -06:00 |
|
verilog_submodules.c
|
remove dead codes for essential gates code generation
|
2019-08-22 10:01:52 -06:00 |
|
verilog_submodules.h
|
start adding submodules of local encoders to multiplexer
|
2019-08-06 14:17:55 -06:00 |
|
verilog_tcl_utils.c
|
Snapshot of progress
|
2019-07-02 10:10:48 -06:00 |
|
verilog_tcl_utils.h
|
Snapshot of progress
|
2019-07-02 10:10:48 -06:00 |
|
verilog_top_netlist_utils.c
|
Latest version explicit
|
2019-07-11 14:33:56 -06:00 |
|
verilog_top_netlist_utils.h
|
Latest version explicit
|
2019-07-11 14:33:56 -06:00 |
|
verilog_top_testbench.c
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
|
verilog_top_testbench.h
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
|
verilog_utils.c
|
add missing files and try to refactor submodule essential
|
2019-08-20 16:13:08 -06:00 |
|
verilog_utils.h
|
add missing files and try to refactor submodule essential
|
2019-08-20 16:13:08 -06:00 |
|
verilog_verification_top_netlist.c
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
|
verilog_verification_top_netlist.h
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_writer_utils.cpp
|
some tuning on Verilog port formatting
|
2019-08-21 23:47:50 -06:00 |
|
verilog_writer_utils.h
|
refactored pass-gate verilog generation
|
2019-08-21 17:33:16 -06:00 |
3f45e6cc87