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fabric_verilog_options.cpp
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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fabric_verilog_options.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_api.cpp
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[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
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2021-06-29 15:26:40 -06:00 |
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verilog_api.h
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[Tool] Deprecate command 'write_verilog_testbench'
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2021-06-09 17:06:01 -06:00 |
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verilog_auxiliary_netlists.cpp
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[Tool] Bug fix for redundant endif in netlists
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2021-06-29 17:02:16 -06:00 |
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verilog_auxiliary_netlists.h
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[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
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2021-06-29 15:26:40 -06:00 |
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verilog_constants.h
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[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
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2021-06-29 15:26:40 -06:00 |
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verilog_decoders.cpp
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_decoders.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_essential_gates.cpp
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_essential_gates.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_formal_random_top_testbench.cpp
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[Tool] Bug fix
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2021-07-02 15:32:30 -06:00 |
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verilog_formal_random_top_testbench.h
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[Tool] Added default net type options to verilog testbench generator command
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2021-06-14 11:37:49 -06:00 |
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verilog_grid.cpp
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_grid.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_lut.cpp
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_lut.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_memory.cpp
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_memory.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_module_writer.cpp
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[Tool] Bug fix for printing single-bit ports in Verilog netlists
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2021-02-28 16:12:57 -07:00 |
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verilog_module_writer.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_mux.cpp
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_mux.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_port_types.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_preconfig_top_module.cpp
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[Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions
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2021-06-29 14:26:33 -06:00 |
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verilog_preconfig_top_module.h
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[Tool] Added default net type options to verilog testbench generator command
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2021-06-14 11:37:49 -06:00 |
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verilog_routing.cpp
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_routing.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_simulation_info_writer.cpp
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[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
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2021-06-29 15:26:40 -06:00 |
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verilog_simulation_info_writer.h
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[Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches
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2021-06-25 10:10:16 -06:00 |
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verilog_submodule.cpp
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_submodule.h
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add architecture decoder (for frame-based config memory) to Verilog writer
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2020-06-11 19:31:09 -06:00 |
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verilog_submodule_utils.cpp
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[Tool] Correct syntax errors for timing definition in verilog for iverilog 10.1
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2021-02-28 17:04:27 -07:00 |
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verilog_submodule_utils.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_testbench_options.cpp
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[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
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2021-06-29 15:42:23 -06:00 |
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verilog_testbench_options.h
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[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
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2021-06-29 15:42:23 -06:00 |
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verilog_testbench_utils.cpp
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[Tool] Bug fix
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2021-07-02 15:32:30 -06:00 |
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verilog_testbench_utils.h
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[Tool] Patch the critical bug in the use of signal polarity in pin constraints
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2021-07-02 15:26:21 -06:00 |
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verilog_top_module.cpp
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_top_module.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_top_testbench.cpp
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[Engine] Register QL memory bank as a legal protocol
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2021-09-09 15:06:51 -07:00 |
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verilog_top_testbench.h
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[Tool] Deprecate command 'write_verilog_testbench'
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2021-06-09 17:06:01 -06:00 |
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verilog_top_testbench_constants.h
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[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
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2021-09-05 21:38:00 -07:00 |
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verilog_top_testbench_memory_bank.cpp
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[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
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2021-09-05 21:38:00 -07:00 |
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verilog_top_testbench_memory_bank.h
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[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
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2021-09-05 21:38:00 -07:00 |
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verilog_wire.cpp
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_wire.h
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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verilog_writer_utils.cpp
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[Engine] Register QL memory bank as a legal protocol
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2021-09-09 15:06:51 -07:00 |
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verilog_writer_utils.h
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[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
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2021-06-03 15:41:11 -06:00 |
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