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check_tile_annotation.cpp
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
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check_tile_annotation.h
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[Tool] Add check codes for tile annotation
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2020-11-11 12:03:13 -07:00 |
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circuit_library_utils.cpp
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[Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers
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2021-09-28 15:56:07 -07:00 |
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circuit_library_utils.h
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[Engine] Add check codes to validate circuit models for BL/WL protocols
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2021-09-23 14:39:16 -07:00 |
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decoder_library_utils.cpp
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[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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decoder_library_utils.h
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[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
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2021-09-10 17:03:44 -07:00 |
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device_rr_gsb_utils.cpp
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device_rr_gsb_utils.h
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fabric_bitstream_utils.cpp
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[FPGA-bitstream] add timer to computing intensive functions
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2022-05-25 14:52:32 +08:00 |
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fabric_bitstream_utils.h
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[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
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2021-10-09 20:39:45 -07:00 |
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fabric_global_port_info_utils.cpp
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[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
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2021-04-18 16:11:11 -06:00 |
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fabric_global_port_info_utils.h
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[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
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2021-04-18 16:11:11 -06:00 |
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lut_utils.cpp
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[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
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2021-02-18 19:37:17 -07:00 |
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lut_utils.h
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[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
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2021-02-18 19:37:17 -07:00 |
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memory_bank_utils.cpp
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[Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken
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2021-09-30 21:20:56 -07:00 |
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memory_bank_utils.h
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[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP
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2021-09-28 17:29:03 -07:00 |
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memory_utils.cpp
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[FPGA-Bitstream] Bug fix in bitstream generator for shift-register-based memory bank
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2021-09-29 22:32:45 -07:00 |
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memory_utils.h
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[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
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2021-09-24 15:15:32 -07:00 |
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module_manager_utils.cpp
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[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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module_manager_utils.h
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[Engine] Merge BL/WLs in the Grid/CB/SB modules
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2021-09-15 11:27:55 -07:00 |
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mux_utils.cpp
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[Engine] Register QL memory bank as a legal protocol
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2021-09-09 15:06:51 -07:00 |
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mux_utils.h
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openfpga_atom_netlist_utils.cpp
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[FPGA-Verilog] Now output atom block name removal has a dedicated function
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2022-02-18 14:30:46 -08:00 |
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openfpga_atom_netlist_utils.h
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[FPGA-Verilog] Now output atom block name removal has a dedicated function
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2022-02-18 14:30:46 -08:00 |
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openfpga_device_grid_utils.cpp
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[Tool] Change the i/o numbering to the clockwise sequence
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2020-11-13 15:00:25 -07:00 |
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openfpga_device_grid_utils.h
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[Tool] Refactor the codes for walking through io blocks
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2020-11-03 13:21:50 -07:00 |
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openfpga_physical_tile_utils.cpp
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[Tool] Extend the support on global tile port for I/O tiles
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2020-11-11 15:09:40 -07:00 |
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openfpga_physical_tile_utils.h
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[Tool] Extend the support on global tile port for I/O tiles
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2020-11-11 15:09:40 -07:00 |
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pb_graph_utils.cpp
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pb_graph_utils.h
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pb_type_utils.cpp
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[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
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2020-09-02 22:16:10 -06:00 |
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pb_type_utils.h
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[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
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2020-09-02 22:16:10 -06:00 |
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physical_pb_utils.cpp
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[Tool] Patch the extended bitstream setting support on mode-select bits
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2021-03-10 21:28:09 -07:00 |
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physical_pb_utils.h
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[Tool] Use dedicated function to identify wire LUT created by repacker
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2021-02-18 19:37:44 -07:00 |
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rr_gsb_utils.cpp
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rr_gsb_utils.h
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simulation_utils.cpp
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[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time
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2021-06-29 09:56:04 -06:00 |
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simulation_utils.h
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[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time
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2021-06-29 09:56:04 -06:00 |
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