56 lines
2.6 KiB
C++
56 lines
2.6 KiB
C++
#ifndef MEMORY_UTILS_H
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#define MEMORY_UTILS_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <vector>
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#include "openfpga_port.h"
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#include "circuit_types.h"
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#include "config_protocol.h"
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#include "module_manager.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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std::map<std::string, BasicPort> generate_mem_module_port2port_map(const BasicPort& config_bus,
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const std::vector<BasicPort>& mem_output_bus_ports,
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const e_circuit_model_design_tech& mem_design_tech,
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const e_config_protocol_type& sram_orgz_type);
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void update_mem_module_config_bus(const e_config_protocol_type& sram_orgz_type,
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const e_circuit_model_design_tech& mem_design_tech,
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const size_t& num_config_bits,
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BasicPort& config_bus);
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bool check_mem_config_bus(const e_config_protocol_type& sram_orgz_type,
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const BasicPort& config_bus,
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const size_t& local_expected_msb);
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std::vector<std::string> generate_sram_port_names(const CircuitLibrary& circuit_lib,
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const CircuitModelId& sram_model,
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const e_config_protocol_type sram_orgz_type);
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size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type,
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const size_t& num_config_bits);
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size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type,
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const size_t& num_config_bits);
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/**
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* @brief Compute the number of configurable children to be skipped for a given configuration protocol
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* For some configuration protocol, the decoders are not counted as configurable children
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* (they are included in the list for bitstream generator usage)
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* The number of decoders depends on the type of configuration protocol.
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*/
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size_t estimate_num_configurable_children_to_skip_by_config_protocol(const ConfigProtocol& config_protocol,
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size_t curr_region_num_config_child);
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} /* end namespace openfpga */
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#endif
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