tangxifan
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433fc73460
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refactored local encoder support for Verilog MUX generation
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2019-09-27 23:10:43 -06:00 |
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tangxifan
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f0949fea2f
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Merge branch 'dev' into refactoring
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2019-09-27 18:09:58 -06:00 |
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tangxifan
|
1e187f3d15
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start adding memory circuit to Switch blocks
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2019-09-27 18:08:37 -06:00 |
AurelienUoU
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640922accd
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-27 16:54:13 -06:00 |
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AurelienUoU
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a93d7e57f7
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Scan chain support in directlist
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2019-09-27 16:53:00 -06:00 |
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tangxifan
|
dbe1625267
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Refactored Verilog wiring for formal verification ports in Switch Blocks
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2019-09-27 13:51:22 -06:00 |
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tangxifan
|
ead014e7d8
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refactoring the configuration bus Verilog generation for MUXes
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2019-09-27 11:47:34 -06:00 |
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AurelienUoU
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056219f180
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Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
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tangxifan
|
009c0d63b5
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refactored the memory bank. Ready to plug-in the test
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2019-09-13 15:05:31 -06:00 |
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tangxifan
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99c30fa7dd
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keep refactoring the memory Verilog generation
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2019-09-13 14:02:04 -06:00 |
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tangxifan
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79fa858f36
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remove unused ports for Verilog modules
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2019-09-11 19:39:59 -06:00 |
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tangxifan
|
0399319212
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refactored LUT Verilog generation
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2019-09-11 17:04:43 -06:00 |
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tangxifan
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62853c092f
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refactoring local encoders. Ready to plug in
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2019-09-10 15:16:29 -06:00 |
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tangxifan
|
59edd49862
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refactored CMOS MUX buffering
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2019-09-06 16:39:34 -06:00 |
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tangxifan
|
bc9d95408e
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bug fixed and refactored intermediate buffer addition
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2019-09-05 16:09:28 -06:00 |
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tangxifan
|
e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
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fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
|
4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
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tangxifan
|
39853408dd
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add recursive global port searching for circuit library
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2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
732e24767f
|
developing module manager
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2019-08-22 23:49:35 -06:00 |
|
tangxifan
|
5a40c6713d
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managed to plug in refactored essential gates, dead codes to be removed
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2019-08-21 21:50:26 -06:00 |
|
tangxifan
|
b08ff465c9
|
refactored pass-gate verilog generation
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2019-08-21 17:33:16 -06:00 |
|
tangxifan
|
9c43b1b753
|
complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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tangxifan
|
a40e5c91ca
|
refactored power-gate inverter
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2019-08-20 21:56:55 -06:00 |
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tangxifan
|
5f55fc7b49
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add missing files and developing essential gates
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2019-08-20 20:43:46 -06:00 |
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tangxifan
|
29104b6fa5
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rework on the circuit model ports and start prototyping mux Verilog generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
a7ac1e4980
|
remame methods in circuit_library
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2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
dcca9f4f0f
|
finish mux graph builders
|
2019-08-20 15:24:52 -06:00 |
|
tangxifan
|
638969c3c9
|
adding mux graph data structures
|
2019-08-20 15:24:52 -06:00 |
|
tangxifan
|
c7526cb43c
|
memory sanitized
|
2019-08-13 14:19:40 -06:00 |
|
tangxifan
|
ef4d15df4e
|
reorganize the libarchfpga repository
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2019-08-13 13:37:35 -06:00 |
|
tangxifan
|
392f579836
|
add linking functions for circuit models and architecture, memory sanitizing is ongoing
|
2019-08-13 13:25:23 -06:00 |
|
tangxifan
|
c56f289d3e
|
add checkers for circuit library
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2019-08-12 16:45:33 -06:00 |
|
tangxifan
|
d4ae160d3a
|
start adding circuit library checkers
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2019-08-12 14:20:11 -06:00 |
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tangxifan
|
fbdab32a2d
|
timing graph for circuit models are working
|
2019-08-10 13:03:24 -06:00 |
|
tangxifan
|
c004699a14
|
complete parsers for ports
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2019-08-09 21:00:41 -06:00 |
|
tangxifan
|
2c7d6e3de4
|
adding port parsers
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2019-08-09 17:48:55 -06:00 |
|
tangxifan
|
f80e58c753
|
developing a in-house tokenizer
|
2019-08-09 16:36:22 -06:00 |
|
tangxifan
|
3d7adb3dd9
|
start developing parsers for delay values
|
2019-08-09 15:52:28 -06:00 |
|
tangxifan
|
6b5ac2e1ef
|
add timing graph builder for circuit models
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2019-08-09 12:45:03 -06:00 |
|
tangxifan
|
c8d04c4f00
|
plug in fast look-up builder
|
2019-08-08 21:20:28 -06:00 |
|
tangxifan
|
158c67075e
|
built a conversion from spice_models to circuit_library and plug in
|
2019-08-08 17:25:27 -06:00 |
|
tangxifan
|
e19485bbb7
|
add more accessors and more to be added when plug into framework
|
2019-08-08 14:16:29 -06:00 |
|
tangxifan
|
ad8c33e1ba
|
complete the mutators
|
2019-08-08 11:33:11 -06:00 |
|
tangxifan
|
5b0c9572c3
|
add mutators for delay_info
|
2019-08-07 21:19:16 -06:00 |
|
tangxifan
|
03a64e2ad8
|
complete the mutators for ports
|
2019-08-07 20:54:27 -06:00 |
|
tangxifan
|
9f8c7a3fc7
|
adding port mutators
|
2019-08-07 17:47:39 -06:00 |
|
tangxifan
|
ed4642a23f
|
adding basic mutators
|
2019-08-07 17:12:05 -06:00 |
|
tangxifan
|
38962c4607
|
adding member functions for circuit library
|
2019-08-07 15:45:27 -06:00 |
|
tangxifan
|
74da4ed51a
|
start creating the class for circuit models
|
2019-08-07 11:38:45 -06:00 |