tangxifan
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56619f9a47
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-07 15:04:05 -07:00 |
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tangxifan
|
477e2119d7
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[test] remove abs paths in golden outputs without time stamps
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2022-09-06 15:24:43 -07:00 |
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tangxifan
|
93ab992187
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[test] update golden outputs without time stamps
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2022-09-06 14:59:00 -07:00 |
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tangxifan
|
561d0a6545
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[test] add more test case to track golden outputs for representative fpga sizes
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2022-09-06 14:04:23 -07:00 |
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tangxifan
|
9e1abf5898
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Merge branch 'master' into vtr_upgrade
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2022-09-01 21:39:14 -07:00 |
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tangxifan
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c48f750f86
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[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
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2022-09-01 20:10:29 -07:00 |
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tangxifan
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c691eb0e95
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Merge branch 'master' into vtr_upgrade
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2022-09-01 15:54:14 -07:00 |
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tangxifan
|
51dc082bd4
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[test] force a fixed routing chan W for no time stamp test case
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2022-09-01 15:02:40 -07:00 |
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tangxifan
|
d86eb04c5d
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[test] now no timestamp test case covers gsb files
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2022-09-01 14:03:51 -07:00 |
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tangxifan
|
71ad0721a1
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Merge branch 'master' into vtr_upgrade
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2022-08-31 13:56:17 -07:00 |
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tangxifan
|
201bca8968
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[test] typo
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2022-08-30 08:59:20 -07:00 |
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tangxifan
|
5f88b9a226
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[test] typo
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2022-08-29 22:41:15 -07:00 |
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tangxifan
|
0b5bdcdbb1
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[test] deploy new test to basic regression tests
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2022-08-29 22:07:56 -07:00 |
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tangxifan
|
069e2b00b1
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[test] add more test cases to validate gsb options
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2022-08-29 22:03:06 -07:00 |
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tangxifan
|
dbacee8a0a
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[script] turn off equivalent for soft adder architecture as we do not expect any routing optimization
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2022-08-27 20:25:50 -07:00 |
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tangxifan
|
ef3381a1b2
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[script] also turn off pb_pin_fixup in vpr for quicklogic tests
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2022-08-27 20:07:49 -07:00 |
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tangxifan
|
b9fade4c76
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[script] turn off the pb_pin_fix_up in vpr run for mcnc and vtr benchmarks
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2022-08-27 20:04:29 -07:00 |
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tangxifan
|
e9d6e7e38a
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[engine] update vtr and enable more debugging info
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2022-08-27 19:12:43 -07:00 |
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tangxifan
|
8d6682c28b
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[test] fixed a bug when removing previous runs
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2022-08-25 16:20:18 -07:00 |
|
tangxifan
|
fa790d50d4
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[script] fixed a bug on wrong path to the ace2 executable
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2022-08-23 10:53:44 -07:00 |
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tangxifan
|
bdb051f787
|
[arch] update arch files
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2022-08-22 18:24:37 -07:00 |
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tangxifan
|
6c44f321e5
|
[script] fixed a bug
|
2022-08-22 18:24:26 -07:00 |
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tangxifan
|
2bbf2f02c9
|
[script] now return status on each arch upgrade task
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2022-08-22 18:23:00 -07:00 |
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tangxifan
|
b6e1175517
|
[script] update doc and avoid modify README.MD when updating arch files
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2022-08-22 18:19:23 -07:00 |
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tangxifan
|
8d45903dc2
|
[script] makefile for vpr arch
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2022-08-22 18:13:48 -07:00 |
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tangxifan
|
3c9c11d451
|
[script] working on formatting
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2022-08-22 18:02:38 -07:00 |
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tangxifan
|
55e765a206
|
[script] slight improve on formatting
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2022-08-22 18:00:14 -07:00 |
|
tangxifan
|
4a7c3fce93
|
[script] debugging format
|
2022-08-22 17:04:30 -07:00 |
|
tangxifan
|
2f5ea0cabb
|
[script] functional arch file converter; need to clean up formatting issues
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2022-08-22 16:40:49 -07:00 |
|
tangxifan
|
4efc506762
|
[script] now change to use minidom and debugging the child removal
|
2022-08-22 16:33:49 -07:00 |
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tangxifan
|
880d7122bf
|
[script] complete code; start debugging on arch file converter
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2022-08-22 12:29:49 -07:00 |
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tangxifan
|
5134ea2233
|
[script] save progress
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2022-08-22 11:00:46 -07:00 |
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tangxifan
|
a61d6a2685
|
[script] developing arch converting script
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2022-08-22 10:34:29 -07:00 |
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tangxifan
|
c0b1d76a5e
|
[script] change default tool paths for OpenFPGA flow scripts
|
2022-08-18 11:02:21 -07:00 |
|
tangxifan
|
6ce1d4804c
|
[test] deploy new test case to basic regression tests
|
2022-08-01 21:05:05 -07:00 |
|
tangxifan
|
9ea4a7c90f
|
[script] fixed a bug
|
2022-08-01 19:18:41 -07:00 |
|
tangxifan
|
8b17bf1b1c
|
[test] add a new test case to validate that .act file is not required when power analysis flow is off
|
2022-08-01 18:44:47 -07:00 |
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tangxifan
|
55c7b75ab6
|
[script] even when power analysis mode is turned off, if users define a act file, still use it
|
2022-08-01 18:13:57 -07:00 |
root
|
0da44ad1fc
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[script] now .act file is no longer required in openfpga_flow/task when power analysis option is off
|
2022-08-02 08:02:28 +08:00 |
|
tangxifan
|
35fe858035
|
[test] fixed a few bugs
|
2022-07-28 12:06:16 -07:00 |
|
tangxifan
|
ca9122ddb9
|
[test] fixed a bug
|
2022-07-28 11:57:47 -07:00 |
|
tangxifan
|
ec31e124b7
|
[test] reworked test case on pcf2place
|
2022-07-28 11:51:56 -07:00 |
|
tangxifan
|
23f98d6a3b
|
[engine] fixed a few bugs
|
2022-07-26 13:55:29 -07:00 |
|
tangxifan
|
353de4546f
|
[test] add 'write_fabric_io_info' command to test cases
|
2022-07-26 13:48:54 -07:00 |
taoli4rs
|
347a29f27c
|
Fix test name in basic regression test script.
|
2022-07-20 21:05:31 -07:00 |
|
taoli4rs
|
3762a3aae4
|
Code clean up based on review.
|
2022-07-20 14:34:44 -07:00 |
|
taoli4rs
|
cfc0d08060
|
Add constrain_pin_location command in openfpga; add full flow test.
|
2022-07-20 11:51:00 -07:00 |
|
tangxifan
|
4b9431b132
|
[test] avoid XML bitstream output when can go beyond github runners' disk space
|
2022-05-25 18:45:26 +08:00 |
|
tangxifan
|
9832722056
|
[test] now add QuickLogic memory bank to fpga bitstream regression tests
|
2022-05-25 11:42:32 +08:00 |
|
tangxifan
|
86347a9d49
|
[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
|
2022-05-25 11:19:49 +08:00 |