tangxifan
|
13f591cacf
|
add new command to disable timing for configure ports of programmable modules
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
ae9f1fbd90
|
critical bug fixed in the disable MUX output
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
99751b84f5
|
bug fix in configuration chain sdc writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
02e86c565a
|
bug fix in configuration chain SDC writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
4c0953415b
|
add configuration chain sdc writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
dad99d13a2
|
bug fixed in SDC timing writer for primitive pb_type
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
b8a79c563d
|
bug fix in the SDC port generation
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
84d24ad075
|
bug fix in pnr sdc grid writer for module paths in hierarchical view
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
99fa51cb49
|
bug fixed in the SDC CB hierarchy writer
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
10e1a4b2fe
|
format fix in the fabric hierarchy and grid SDC hierarchy to be complaint to YAML format
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
cc6d988872
|
bug fix in grid SDC generator
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
b167c85980
|
fully expand grid hierarchy in SDC writer
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
55518f4cec
|
minor fix in the sdc hierarchy writer for grids
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
b57a90a6ca
|
add SDC hierarchy writer for grids and now support flatten hierarchy in grid timing constraints
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
d9dc7160a7
|
minor fix on the hierarchy writer in SDC generator
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
17c254a370
|
add missing file to follow up the previous commit
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
c651df6421
|
add hierarchy writer to SDC generator
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
0985c720e9
|
remove regexp in SDC generation.
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
8726c618eb
|
add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
0e44cf3ea3
|
now SDC to disable routing multiplexer outputs can use wildcards
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
609115e51f
|
now hierarchical SDC generation is applicable to CB timing constraints
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
7e82c23f52
|
now add SDC generator supports both hierarchical and flatten in writing timing constraints
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
7503c58fb2
|
small fix on SDC generator for SB which do not exist in FPGA
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
d0793d9029
|
now disable_sb_output support wildcard
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
8695c5ee78
|
add options to use general-purpose wildcards in SDC generator
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
facd87dafe
|
use wildcard in SDC generation for multiple-instanced-blocks
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
2e3054f79a
|
bug fixed for SDC generation for LUTs
|
2020-04-21 14:34:51 -06:00 |
|
tangxifan
|
68b7991a46
|
bug fixed for sdc on memory blocks
|
2020-04-21 13:37:56 -06:00 |
|
tangxifan
|
3f1fb70d16
|
FPGA SDC now constrain max and min delay for primitive modules in grids
|
2020-04-21 11:00:28 -06:00 |
|
tangxifan
|
c2804a4c1f
|
bug fix for RC delay computing in SDC generation
|
2020-04-20 22:20:00 -06:00 |
|
tangxifan
|
1a8968cb37
|
now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML
|
2020-04-20 21:12:51 -06:00 |
|
tangxifan
|
2ffd174e6a
|
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
|
2020-04-15 15:48:33 -06:00 |
|
tangxifan
|
e6c896d583
|
now inout must be global port and I/O port so that it will appear in the top-level module
|
2020-04-08 16:54:08 -06:00 |
|
tangxifan
|
decc1dc4b2
|
debugged global gp input/output port support
|
2020-04-05 17:39:30 -06:00 |
|
tangxifan
|
ff9cc50527
|
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
|
2020-03-27 20:09:50 -06:00 |
|
tangxifan
|
e601a648cc
|
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
|
2020-03-27 19:07:34 -06:00 |
|
tangxifan
|
329b0a9cf1
|
add options to enable SDC constraints on zero-delay paths
|
2020-03-25 15:55:30 -06:00 |
|
tangxifan
|
4a0128f240
|
minor fix on the SDC format
|
2020-03-25 14:46:31 -06:00 |
|
tangxifan
|
c2e5d6b8e2
|
add options to dsiable SDC for non-clock global ports
|
2020-03-25 14:38:13 -06:00 |
|
tangxifan
|
8f35f191eb
|
use the formalized function in FPGA-SDC to identify direct connection
|
2020-03-21 11:42:00 -06:00 |
|
tangxifan
|
682b667a3c
|
minor bug fix for direct connection in FPGA-SDC
|
2020-03-20 21:44:01 -06:00 |
|
tangxifan
|
7fcd27e000
|
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
|
2020-03-03 12:29:58 -07:00 |
|
tangxifan
|
3241d8bd37
|
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
|
2020-03-02 19:54:18 -07:00 |
|
tangxifan
|
037c7e5c43
|
adapt top-level function for analysis SDC writer
|
2020-03-02 17:58:44 -07:00 |
|
tangxifan
|
24f7416c71
|
adapt analysis SDC writer for grids
|
2020-03-02 17:15:01 -07:00 |
|
tangxifan
|
6474183539
|
adapt analysis SDC writer for routing modules
|
2020-03-02 14:29:58 -07:00 |
|
tangxifan
|
543cff58b9
|
start porting analysis SDC writer
|
2020-03-02 13:44:08 -07:00 |
|
tangxifan
|
de8425874c
|
use user defined critical path delay in SDC generation
|
2020-02-28 11:24:39 -07:00 |
|
tangxifan
|
092e10afda
|
bring pnr sdc generator online and fixed minor bugs in bitstream writing
|
2020-02-28 11:14:50 -07:00 |
|
tangxifan
|
e45fa18c4c
|
adapt PnR SDC writer
|
2020-02-28 10:06:35 -07:00 |