tangxifan
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f116351831
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add instance name for each pb graph node
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2019-10-26 17:25:45 -06:00 |
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tangxifan
|
7649d9228e
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fixed bugs in refactored bitstream generation
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2019-10-26 16:40:14 -06:00 |
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tangxifan
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0a9c89be0b
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add bitstream writers and start debugging
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2019-10-26 12:41:23 -06:00 |
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tangxifan
|
3310bac65b
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refactored grid bitstream generation
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2019-10-25 21:49:47 -06:00 |
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tangxifan
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4b7a9dfa63
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add instance name correlation between module and bitstream generation
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2019-10-25 13:06:48 -06:00 |
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tangxifan
|
0b687669c8
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affliate configuration bitstream to sb blocks
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2019-10-25 10:42:12 -06:00 |
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tangxifan
|
838173f3c4
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start refactoring bitstream generator
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2019-10-24 21:01:11 -06:00 |
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tangxifan
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13c62fdcf8
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add more methods to bitstream manager (renamed from bitstream context)
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2019-10-24 15:43:29 -06:00 |
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tangxifan
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f26dbfe080
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add instance name for top-level modules to ease readability
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2019-10-23 20:24:52 -06:00 |
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tangxifan
|
2787a07f0d
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start refactoring bitstream generation
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2019-10-23 17:34:21 -06:00 |
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tangxifan
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a18f1305cd
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add configurable child list to module manager
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2019-10-23 15:44:13 -06:00 |
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tangxifan
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12162a02bc
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critical bug fixing for compact routing hierarchy and top module generation
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2019-10-23 14:20:04 -06:00 |
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tangxifan
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fb2f003d5b
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add top module generation and refactored verilog generation for top module
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2019-10-23 12:16:58 -06:00 |
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tangxifan
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dafab3907e
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refactored routing module generation and verilog writing
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2019-10-23 11:46:55 -06:00 |
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tangxifan
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9cf8683acd
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add module generation for memories
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2019-10-22 15:31:08 -06:00 |
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tangxifan
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f002f7e30f
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add const 0 and 1 module Verilog generation
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2019-10-21 14:17:09 -06:00 |
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tangxifan
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b2f57ecf81
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plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
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2019-10-21 00:00:30 -06:00 |
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tangxifan
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520e145af2
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move mux_lib to fpga_x2p_setup
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2019-10-19 19:13:52 -06:00 |
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tangxifan
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04f0fbebf7
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plug in module graph to feed verilog writers
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2019-10-18 21:59:22 -06:00 |
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tangxifan
|
7c1bce4b59
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add module builders for essential gates
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2019-10-18 20:41:05 -06:00 |
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tangxifan
|
3b82d62d03
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start developing module graph builders
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2019-10-18 20:02:02 -06:00 |
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tangxifan
|
db38f21412
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add netlist manager class
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2019-10-18 17:59:03 -06:00 |
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tangxifan
|
8c1158fc5c
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refactor memory organization at the top-level module
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2019-10-18 15:33:25 -06:00 |
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tangxifan
|
4171a674b1
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refactored clb2clb direct connects for cross-column/row
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2019-10-17 23:06:59 -06:00 |
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tangxifan
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190449c06f
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refactoring top-level module with clb2clb direct connection
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2019-10-17 17:29:04 -06:00 |
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tangxifan
|
c9d8311a93
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bug fixing for grid-gsb connections in top module when using compact routing
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2019-10-15 18:00:55 -06:00 |
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tangxifan
|
6a13120208
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rename grid modules to be clear
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2019-10-15 16:28:46 -06:00 |
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tangxifan
|
071757dc52
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add module nets to connect grids and sbs
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2019-10-15 16:08:51 -06:00 |
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tangxifan
|
f779ad7ecf
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bug fixing for global and gpio port wiring; start refactoring top-level module
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2019-10-14 15:53:04 -06:00 |
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tangxifan
|
6793c67c8d
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refactored pb_type and grid Verilog generation
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2019-10-13 21:07:30 -06:00 |
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tangxifan
|
b581399761
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add memory ports and nets to intermediate pb_types
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2019-10-13 17:45:32 -06:00 |
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tangxifan
|
cab4bd6807
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add gpio ports to pb_type modules
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2019-10-13 16:23:22 -06:00 |
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tangxifan
|
d1948c82eb
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Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
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2019-10-11 21:43:47 -06:00 |
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tangxifan
|
b3ca0d32a4
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remove configuration bus naming dependency on SRAM circuit models
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2019-10-11 19:47:36 -06:00 |
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tangxifan
|
73a5977e0d
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Debugged Verilog generation for primitive pb_types
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2019-10-11 18:00:37 -06:00 |
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tangxifan
|
50f7d1eae3
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bug fixing in Verilog port merging and instanciation
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2019-10-11 14:20:04 -06:00 |
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tangxifan
|
663b1b7665
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refactorint net addition for configuration signals in module graph
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2019-10-11 13:07:14 -06:00 |
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tangxifan
|
c9950162d1
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start plug in new Verilog writer. Start debugging
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2019-10-10 22:02:46 -06:00 |
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tangxifan
|
1f650aac73
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add local direct connection Verilog code generation
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2019-10-10 20:54:31 -06:00 |
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tangxifan
|
f2b3341d87
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developing verilog writer for generic module graph
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2019-10-10 20:09:55 -06:00 |
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tangxifan
|
e5956467fd
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developing verilog writer for modules
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2019-10-10 14:43:32 -06:00 |
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tangxifan
|
edad988ebb
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add net accessor and mutators to module manager
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2019-10-09 21:14:30 -06:00 |
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tangxifan
|
557d8b60f3
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start implementing module graph-based connection
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2019-10-09 20:30:16 -06:00 |
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tangxifan
|
9cb6e64ab3
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refactoring instanciation inside primitive pb_type Verilog module
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2019-10-08 21:29:42 -06:00 |
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tangxifan
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6f42aac626
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add wire connection in Verilog module declaration
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2019-10-08 20:14:38 -06:00 |
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tangxifan
|
ea2942640e
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refactored port addition for pb_types in Verilog generation
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2019-10-08 14:03:17 -06:00 |
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tangxifan
|
512e9f4e8e
|
refactoring Verilog generation for primitive pb_types
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2019-10-08 12:10:26 -06:00 |
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tangxifan
|
173b886314
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add module name generation for pb_types
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2019-10-07 21:09:54 -06:00 |
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tangxifan
|
3ca6f08aa4
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start refactoring physical block Verilog generation
|
2019-10-06 19:27:55 -06:00 |
|
tangxifan
|
1e183e7885
|
refactored shared config bits calculation
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2019-10-06 16:57:53 -06:00 |