Commit Graph

2974 Commits

Author SHA1 Message Date
Baudouin Chauviere 1932d00309 Correction of the SDC to remove global clocks 2019-05-30 15:04:21 -06:00
AurelienUoU ba05a08ef0 Path correction in tech debugging + correction of yosys rewrite file in fpga_flow 2019-05-30 09:52:19 -06:00
AurelienUoU 0e820d38ea Speedup the install on travis 2019-05-29 16:53:35 -06:00
AurelienUoU 46fa1197b0 Test reading tech file 2019-05-29 16:43:56 -06:00
AurelienUoU 74ee6bad7f Update spice path in architecture 2019-05-29 10:08:58 -06:00
tangxifan 5b15a746d3 add num_driver_nodes to Switch Block XML writter 2019-05-28 20:52:33 -06:00
tangxifan 5ed076dfb4 fixed a critical bug in rotating 2019-05-28 17:55:09 -06:00
tangxifan 9cc5518d5a keep adding segment information for SB XML outputter 2019-05-28 15:59:55 -06:00
tangxifan e7e18eb4c1 Add more information in SB XML outputter 2019-05-28 15:56:41 -06:00
tangxifan ca402f87e5 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-28 15:19:48 -06:00
tangxifan ca363da30c add options to specify output directory of SB XML 2019-05-28 15:19:10 -06:00
AurelienUoU 4ef25a7550 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-28 15:03:40 -06:00
AurelienUoU f934f6f0a3 Debug step 2019-05-28 15:01:16 -06:00
tangxifan 6b51b42ee7 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-28 14:53:44 -06:00
tangxifan af91fca1e0 add rr_blocks XML writer to help debugging Switch Block Rotation 2019-05-28 14:52:44 -06:00
Baudouin Chauviere 3da216f297 correction Null issue for the flat model 2019-05-28 14:15:24 -06:00
AurelienUoU ffdcd4bb9c Path correction 2 2019-05-28 11:59:09 -06:00
tangxifan c75ffa858b Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-28 11:26:16 -06:00
tangxifan 6f30d3ad05 support rotation on segment groups inside RRChan and improve rotatable mirror searching 2019-05-28 11:25:16 -06:00
AurelienUoU 20f80a73e7 Correct path to tech files 2019-05-28 11:24:03 -06:00
AurelienUoU e0717369e1 Re-insert power option in regression test 2019-05-28 09:48:03 -06:00
tangxifan 0f5666ea11 fixed the bug in mirror node direction 2019-05-27 21:58:21 -06:00
tangxifan eece161d58 keep debugging on Switch Block rotation 2019-05-27 21:10:30 -06:00
tangxifan 5720217cfd Add copy constructor for RRChan, RRSwitchBlock etc. 2019-05-27 15:44:34 -06:00
tangxifan 1bea9870fc developed new rotating methods for RRSwitchBlocks, debugging ongoing 2019-05-26 23:35:30 -06:00
tangxifan 4b852afeac skip rotating mirror detection which is too time-consuming 2019-05-25 23:41:46 -06:00
tangxifan 22e71f5847 Add rotate one side of switch block functionality 2019-05-25 22:48:07 -06:00
tangxifan 858a323228 Add more support for rotating Switch Blocks 2019-05-25 21:26:35 -06:00
tangxifan 2eab0b1c1c update unique_mirror search algorithm for Switch Blocks 2019-05-25 19:54:15 -06:00
tangxifan d3eae80e64 implemented an native way in finding rotable Switch blocks 2019-05-25 19:37:18 -06:00
tangxifan ae0248fbc6 debugging SwitchBlock rotating 2019-05-24 23:10:30 -06:00
tangxifan 9adc2945c8 add rotate functionality for RRSwitchBlock 2019-05-24 21:40:16 -06:00
tangxifan 02b48d036d clean warnings 2019-05-24 16:48:08 -06:00
tangxifan 2c46da6888 clean-up warnings Verilog routing generator 2019-05-24 16:29:17 -06:00
tangxifan 27b996337a fixed a critical bug in Compact Verilog generation for SB/CBs 2019-05-24 16:14:46 -06:00
tangxifan 1ade1f1d3f update SDC generator disabled_unused_mux by using RRSwitchBlock 2019-05-24 15:42:00 -06:00
tangxifan f27b88db8d Use RRChan in SDC generator to replace old data structures 2019-05-24 15:34:56 -06:00
tangxifan 27c234711e clean up warnings in SDC pb_type generator 2019-05-24 15:23:38 -06:00
tangxifan 924136e7a2 Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info 2019-05-24 15:10:08 -06:00
tangxifan 994b90ae53 updated report_timing for using RRSwitchBlock 2019-05-24 14:25:51 -06:00
tangxifan eef1312325 updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
tangxifan 5de38f023c Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-23 21:53:16 -06:00
tangxifan 8f4f590ff9 update Verilog compact_netlist outputter with RRSwitchBlock classes 2019-05-23 21:52:12 -06:00
AurelienUoU d3f0ab59c2 Remove -power token until option is fixed 2019-05-23 19:26:25 -06:00
AurelienUoU 3811c18953 Correct syntax error in tokens of regression_fpga_flow.sh 2019-05-23 18:33:47 -06:00
AurelienUoU 1018134726 Update yosys to latest version + add simulation in fpga_flow 2019-05-23 17:55:49 -06:00
tangxifan ee1a24d4ba Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-23 17:38:35 -06:00
tangxifan ea8c36ce6e upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
AurelienUoU 555570c15e Update Yosys from version 0.7 to version 0.8 2019-05-23 16:03:08 -06:00
tangxifan ec70bcee99 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-22 22:05:46 -06:00